2020-10-03

五分频的verilog

1.程序
module divider(clk_in,clk_out,rst)
input clk_in,rst;
output clk_out;
reg clk_out;
reg [2:0]count;
always@(posedge clk_in or negedge rst)
begin
if(!rst)
begin
count<=0;
clk_out<=0;
end
else if(count等于4）//
begin
count<=0;
clk_out<=~clk_out;
end
else if(count==2)
begin
clk_out<=~clk_out;
count<=count+1;
end
else
count<=count+1;
endendmodule

2.testbench
`timescale 1 us/ 1 ps
module divider_tb;
reg clk_in;
reg rst;
// wires
wire clk_out;

// assign statements (if any)
divider i1 (
// port map - connection between master ports and signals/registers
.clk_in(clk_in),
.clk_out(clk_out),
.rst(rst)
);
always #1 clk_in=~clk_in;
initial
begin
#0 rst=0;clk_in=0;
#20 rst=1;
end
endmodule

3.仿真图