Verilog刷题HDLBits——Fsm3s

题目描述

See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)

代码

module top_module(
    input clk,
    input in,
    input reset,
    output out); //

    parameter A=0,B=1,C=2,D=3;
    reg[1:0] state,next_state;
    // State transition logic
    always@(*)
        case(state)
            A: next_state=(in==1)?B:A;
            B: next_state=(in==1)?B:C;
            C: next_state=(in==1)?D:A;
            D: next_state=(in==1)?B:C;
        endcase

    // State flip-flops with synchronous reset'
    always@(posedge clk)
        if(reset)
            state<=A;
    	else
            state<=next_state;

    // Output logic
    assign out = (state==D);

endmodule

结果