SV数据类型练习

主模块：

module data_type;
//开关闭合状态，各模块均未开始
bit b_signed_vs_unsigned = 0;
bit b_bit_vs_logic = 0;
bit b_enum_type = 0;
bit b_struct_type = 0;

initial begin:signed_vs_unsigned
    byte b0;//有符号
    bit [7:0] b1;//无符号
    wait(b_signed_vs_unsigned == 1);
        $display("signed_vs_unsigned process block started");
    b0 = 'b1000_0000;
    $display("byte variable b0 = %d",b0);//-128
    b1 = b0;
    $display("bit vector varible b1 = %d",b1);//128
    end

initial begin:bit_vs_logic
    bit [1:0] v1;//二值逻辑
    logic [1:0] v2;//四值逻辑
    wait(b_bit_vs_logic == 1);   
        $display("bit_vs_logic process block started");
    v2 = 2'b1;
    $display("logic variable v2 = %b",v2);
    v1 = v2;
    $display("bit vector varible v1 = %b",v1);//v1=2'b01
    v2 = 2'b0;
    $display("logic variable v2 = %b",v2);
    v1 = v2;
    $display("bit vector varible v1 = %b",v1);  //v1=2'b00
    v2 = 2'bx;
    $display("logic variable v2 = %b",v2);
    v1 = v2;
    $display("bit vector varible v1 = %b",v1); //v1=2'b00
    v2 = 2'bz;
    $display("logic variable v2 = %b",v2);
    v1 = v2;
    $display("bit vector varible v1 = %b",v1);  //v1=2'b00
end

initial begin:enum_type//枚举类型
typedef enum{IDLE,START,PROC,END}state_t;//依次默认为0，1，2，3
state_t st1,st2;//枚举变量
wait(b_enum_type == 1);
    $display("bit_vs_logic process block started");
//三种打印st1的方式
st1 = IDLE;
$display("st1 value = %0d (int)",st1);//0(int)
$display("st1 value = %s (string)",st1);//IDLE(string)
$display("st1 value = %s (string)",st1.name());//IDLE(string)

//枚举类型赋值
st2 = state_t'(1);
$display("st1 value = %0d (int)",st2);//1(int)
$display("st1 value = %s (string)",st2.name());//START(string)

//数值4不在枚举类型中，所以打印不出来枚举名称，可以赋值，但是程序也不会报错
st2 = state_t'(4);
$display("st1 value = %0d (int)",st2);//4(int)
$display("st1 value = %s (string)",st2.name());// 空
end

initial begin:struct_type//结构体类型
    typedef struct{
        bit [7:0] addr;
        bit [31:0] data;
        bit is_write;
        int id;
}trans_t;
trans_t t1,t2,t3;//结构体变量
wait(b_struct_type == 1);
$display("struct_type process block started");
t1 = '{'h10,'h1122_3344,'b1,'h1000};//结构体赋值默认为非组合，所以需要分别对addr,data,is_write,id赋值
$display("t1 data content is %p",t1);//%p用来打印数组

t2.addr = 'h20;
t2.data = 'h5566_7788;
t2.is_write = 'b0;
t2.id = 'h2000;
$display("t2 data content is %p",t2);

t3 = t2;
t3.data = 'h99AA_BBCC;
t3.id = 'h3000;
$display("t2 data content is %p",t3);
$display("t2 data content is %p",t2);
end

endmodule

仿真结果1：

bit b_signed_vs_unsigned = 1;

仿真结果2：

bit b_bit_vs_logic = 1;

仿真结果3：

bit b_enum_type = 1;

仿真结果4：

bit b_struct_type = 1;