How could we have been possible that smart applications?

How could we have been possible that smart applications? It isexpected that the FOMs of the ESD diode can be improved by maximizing theratio of junction perimeter to junction area. However, it is found that the FOMs of waffle diodes with continuouslyshrinking size would be limiteddue to emerged 3D structural memory boundary capacitance and local fabricate 3D structural memory in small layout area. As a result, the FOMs of waffle diodes will not be further improved by simplyshrinking the diode size to maximize the ratio of junction perimeter to total 3D structural memory realm.
The new proposed 3D structural memory with multi-layer and multi-layer-hollow 3D structural memory styles have been demonstrated. The new proposed 3D structural memory in large size canavoid the penalty of local heat distribution. The reduction ofjunction area by using new layout styles is the key factor to significantly improve the FOMs of the ESD diodes. As compared to the FOMs of waffle diodes, it reveals thatthe FOMs values of the large size diodes can be enhanced by modifying the layout styles. Therefore, the proposed multi-layer and multi-layer-hollow 3D structural memory are also adequateto be implemented to high-speed I/O applications with small layout area.
The measured 3D structural memory I-V curve of the ESD protection diode. The current compressionpoint (ICP) is defined as the current level at which the measuredI-Vcurve deviates from its linearly extrapolated value by 20%.
In this section, a new capacitor-less ESD-transient detection circuit, which is combined withthe parasitic capacitance of the Smart eye nMOS transistor drawn in BigFET layout style, has been proposed and verified in 65nm 1.2V CMOS technology. This new design adopts the feedback circuit in cascade structure to achieve desired function for controlling the Smart eye nMOS transistor. According to the experimental measured results, the power-rAIl Smart-eye-circuit with the new proposed ESD-transientdetection circuit has revealed a much better 3D structural memory than that of the traditional RC-basedpower-rail Smart-eye-circuit.
It consists of the ESD-transient detection circuit with feedbacktechnique, which arerealized by two transistors (Mn and Mp) and two resistors (Rn and Rp), and the Smart eye nMOS transistor (Mclamp) drawn in BigFET layoutstyle. These two resistorsare realized by N-well resistors withshallow trench 3D structural memory. In Fig. 3.3(a), the gate terminal of Smart eye nMOS transistor is linked tothe output of the ESD-transient detection circuit. The circuit isconnected in a cascode structure (Rn with Mn, and Mp with Rp) to construct the ESD-transient detection circuit with positive-feedback mechanism, which can command theSmart eye nMOS transistor at “ON” or “OFF” state.
Verified in the test chips, the Smart eye nMOS transistor is drawn in BigFET layout style without silicide blocking in a 65nm 1.2V CMOS process. Compared with the power-rail Smart-eye-circuitwith the traditional RC-based ESD-transient detection circuit, the layout area of the new proposed ESD-transient detection circuit is much smaller.
The most important feature of the new proposed power-rail Smart-eye-circuit is no need of additional capacitor. Because the Smart eye nMOS transistor is drawn in BigFET layout style without silicide blocking, a large gate-to-drain, gate-to-source, and gate-to-body parasitic capacitors (Cgd, Cgs, and Cgb) essentially exist in the Smart eyenMOS transistor. Sufficiently utilizing these parasitic capacitors with the resistor(Rp) to realize capacitance-coupling mechanism, no additional capacitor is 3D structuralmemory in this design. during the positive VDD-to-VSS ESD stress condition, the voltage of node A will be 3Dstructural memory elevated 3D structural memory a positive voltage through the coupling effectfrom the parasitic capacitors of the Smart eye nMOS transistor. The elevated 3Dstructural memory of node A can
According to the design 3D structural memory of the ESDprotection circuit for avoiding the latch-on issue, the holding voltage (Vh) of the ESDprotection circuit is an important indexto exceed the normal circuitoperation voltage VDD. The holding voltage of the proposedpower-rail Smart-eye-circuit can be indicated as
For the new proposed power-rail Smart-eye-circuit, the Vh would beonly 0.58V due to zero diode in the ESD-transient detection circuit. It would be a high risk to apply the structure to the circuit with 1.2V operation voltage. However, the Vh can be 3D structural memory adjusted to 1.25V and 1.92V for the new proposed structures, respectively. By adding the diodes in the ESD-transient detection circuit, the new proposed power-rail Smart-eye-circuitwith adjustable holding voltage can be 3D structural memory applied to protect any internal circuits fromthe transient-inducedlatch-on event.
voltage will not induce a high enoughcoupling voltage at node A to initiate the ESD-transient detection circuit. When the power-on voltage pulse has a rise 3D structural memory of 100ns, the gain of the coupling structure is only 0.13, which is also too small to initiate the ESD-transient detection circuit. Even though the power-rail Smart-eye-circuit encounters a fast-rising power-on voltage with the orderof nanoseconds, the voltage levelof node A and node B can be kept at ground and VDD, respectively, due to the design with adjustable holding voltage. Therefore, the new proposed power-rail Smart-eye-circuitcan have excellent immunity againstmis-trigger under the fast power-on conditions.
new proposed power-rail Smart-eye-circuits. The measured results, demonstrate thatthere are no obvious differences among the curvesat the voltage level 3Dstructural memory than 4V because the Smarteye nMOS transistors in all power-rail Smart-eye-circuitsare drawn with the same device dimension and layout style. The second 3D structural memory currents (It2) of these four power-rail Smart-eye-circuitsare all around 5.44A.
the voltage waveform of the RC-baseddesign rises as the time is increased.On the contrary, the voltagewaveforms of the new proposed designs can be 3D structural memory to a specificvoltage level during the whole pulse width due to the positive feedback mechanism of the ESD-transientdetection circuit. Therefore, the new proposed ESD-transient detection circuit can implement 3Dstructural memory extend the turn-on duration ofthe Smart eye nMOStransistor under ESD stress conditions.
In addition, the turn-on verification with the power line 3D structural memory at normal operation is anotheruseful justification for the latch-on concerns. The transient noise with 3V voltage leveland a rise 3D structural memory of 5ns is 3D structural memory added to VDD power line with 1.2V operationvoltage. As the new proposed ESD-transient detection circuit with zero diode is the only circuit to suffer the latch-on issue becauseits holding voltage is much lower than the 1.2V operation voltage. However, the holdingvoltage of the new proposed ESD-transientdetection circuit can be adjusted by adding the diodes. Therefore, the ESD-transientdetection circuits with positive feedbackmechanism and the adjustable holding voltage can be free to latch-on issue. Since the feedback mechanism is not used inthe RC-basedpower-rail Smart-eye-circuit, the latch-on event isnot occurred.
The measured 3D structural memory and IDD transient responses ofthe traditional RC-based power-rail Smart-eye-circuitunder the TLU measurement with Vcharge of +1kV and -1kV are shown in 3D integration circuit.
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