多功能数字钟之分频器构造（VHDL）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
entity div is
port(            clk:in std_logic;
  hz_1,hz_128,hz_512:out std_logic);
end div;
 
architecture q of div is
signal q:std_logic_vector(9 downto 0);

begin
 process(clk)
  begin
   if(rising_edge(clk)) then
   q<=q+1;
   end if;
 end process;
 hz_1<=q(9);
 hz_128<=q(2);
 hz_512<=q(0);
end q;