数码管动态显示电路设计（VHDL）

VHDL数码管动态显示电路

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一、动态数码管是什么？

七段数码管是电子开发过程中常用的输出显示设备。实验箱中七段数码管采用共阴极，当数码管的中的哪一个段被输入高电平，则相应的这一段被点亮。

四位一体的七段数码管在单个静态数码管的基础上加入了用于选择哪一位数码管的位选信号端口。

八个数码管的a、b、c、d、e、f、g、h、dp都连在了一起，8个数码管分别由各自的位选信号来控制，被选通的数码管显示数据，其余关闭。

这样对于一组数码管动态扫描显示需要有两组信号来控制：一组是字段输出口输出的字形代码，用来控制显示的字形，称为段码；

另一组是位输出口的控制信号，用来选择第几个数码管工作，称为位码。

二、VHDL实现代码

1.根据 电路图完成VHDL描述：

代码如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dtsm is
 port(clk:in std_logic;
   key:in std_logic_vector(3 downto 0);
ledag:out std_logic_vector(6 downto 0);
sel:out std_logic_vector(2 downto 0)
);
 end dtsm;
 architecture beha of dtsm is
 begin
 process(clk)
  variable count:std_logic_vector(2 downto 0);
begin
 if (clk'event and clk='1') then
  count:=count+1;
end if;
  sel<=count;
 end process;
 process(key)
 begin
 case key is
when"0000"=>ledag<="0111111";
when"0001"=>ledag<="0000110";
when"0010"=>ledag<="1011011";
when"0011"=>ledag<="1001111";
when"0100"=>ledag<="1100110";
when"0101"=>ledag<="1101101";
when"0110"=>ledag<="1111101";
when"0111"=>ledag<="0000111"; 
when"1000"=>ledag<="1111111";
when"1001"=>ledag<="1100111";
when"1010"=>ledag<="1110111";
when"1011"=>ledag<="1111100";
when"1100"=>ledag<="0111001";
when"1101"=>ledag<="0111110";
when"1110"=>ledag<="1111001";
when"1111"=>ledag<="1110001";
when others=>null; 
end case;
 end process;
end beha;

2.8个数码管显示不同的数字或符号

代码如下：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity dtsm is

 port(clk:in std_logic;

   key:in std_logic_vector(3 downto 0);

ledag:out std_logic_vector(6 downto 0);

sel:out std_logic_vector(2 downto 0)

);

 end dtsm;

 architecture beha of dtsm is

signal ww:std_logic_vector(2 downto 0);

 begin

 process(clk)

  variable count:std_logic_vector(2 downto 0);

begin

 if (clk'event and clk='1') then

  count:=count+1;

end if;

  sel<=count;

  ww<=count;

 end process;

 process(ww)

 begin

 case ww is

when"000"=>ledag<="0111111";

when"001"=>ledag<="0000110";

when"010"=>ledag<="1011011";

when"011"=>ledag<="1001111";

when"100"=>ledag<="1100110";

when"101"=>ledag<="1101101";

when"110"=>ledag<="1111101";

when"111"=>ledag<="0000111"; 

when others=>null; 

end case;

 end process;

end beha;

3.管脚锁定

该处使用的url网络请求的数据。

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总结

由于count与时钟信号有关，如下

  variable count:std_logic_vector(2 downto 0);

begin

 if (clk'event and clk='1') then

  count:=count+1;

end if;

  sel<=count;

  ww<=count;

 end process;

 process(ww)

 begin

 case ww is

when"000"=>ledag<="0111111";

when"001"=>ledag<="0000110";

when"010"=>ledag<="1011011";

when"011"=>ledag<="1001111";

when"100"=>ledag<="1100110";

when"101"=>ledag<="1101101";

when"110"=>ledag<="1111101";

when"111"=>ledag<="0000111"; 

when others=>null; 

end case;

 end process;

当时钟频率到达100HZ时即可看到，不同数码管显示不同的数字/字符