基于FPGA的RISC_V五级流水设计---存储设计

通过上篇文章对cpu的大致认识，就可以开始RTL设计，这次设计不会细致的讲解，希望大家可以自己看书学习，强烈推荐的一本书。通过计组书的学习，不仅你会理解cpu的架构，也会对系统化的设计有更深层次的认识。本次设计为存储器的设计
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寄存器堆设计

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端口声明如下

	input          clk                       ;
	input          rst_n                     ;
    input  [4:0]   read_reg1                 ;
	input  [4:0]   read_reg2                 ;
	input  [4:0]   write_reg                 ;
	input  [31:0]  write_data                ;
	input          regwrite                  ;
	output  reg [31:0] read_data1            ;
	output  reg [31:0] read_data2            ;

时钟采用50Mhz，根据指令将rd1，rd2的数据通过read_data1、read_data2输出，当regwrite为1，表示有数据写入，将数据写入目标寄存器。这里写入数据采用了在时钟下降沿写入，可以有效避免结构冒险刚开始写并没有采用此方法，虽然仿真正确，但在板级验证产生错误。代码如下

always@(negedge clk or negedge rst_n)
	if(!rst_n)begin
	x0       <=       32'd0   ;
	x1       <=       32'd0   ;
	x2       <=       32'd0   ;
	x3       <=       32'd0   ;
	x4       <=       32'd0   ;
	x5       <=       32'd1   ;
	x6       <=       32'd2   ;
	x7       <=       32'd0   ;
	x8       <=       32'd0   ;
	x9       <=       32'd0   ;
	x10      <=       32'd5   ;
	x11      <=       32'd0   ;
	x12      <=       32'd0   ;
	x13      <=       32'd0   ;
	x14      <=       32'd0   ;
	x15      <=       32'd0   ;
	x16      <=       32'd0   ;
	x17      <=       32'd0   ;
	x18      <=       32'd0   ;
	x19      <=       32'd0   ;
	x20      <=       32'd0   ;
	x21      <=       32'd0   ;
	x22      <=       32'd0   ;
	x23      <=       32'd0   ;
	x24      <=       32'd0   ;
	x25      <=       32'd0   ;
	x26      <=       32'd0   ;
	x27      <=       32'd0   ;
	x28      <=       32'd0   ;
	x29      <=       32'd0   ;
	x30      <=       32'd0   ;
	x31      <=       32'd0   ;
	end
	else if(regwrite)begin
	case(write_reg)
	5'd0        :      x0       <=       'd0   ;
	5'd1        :      x1       <=       write_data   ;
	5'd2        :      x2       <=       write_data   ;
	5'd3        :      x3       <=       write_data   ;
	5'd4        :      x4       <=       write_data   ;
	5'd5        :      x5       <=       write_data   ;
	5'd6        :      x6       <=       write_data   ;
	5'd7        :      x7       <=       write_data   ;
	5'd8        :      x8       <=       write_data   ;
	5'd9        :      x9       <=       write_data   ;
	5'd10       :      x10      <=       write_data   ;
	5'd11       :      x11      <=       write_data   ;
	5'd12       :      x12      <=       write_data   ;
	5'd13       :      x13      <=       write_data   ;
	5'd14       :      x14      <=       write_data   ;
	5'd15       :      x15      <=       write_data   ;
	5'd16       :      x16      <=       write_data   ;
	5'd17       :      x17      <=       write_data   ;
	5'd18       :      x18      <=       write_data   ;
	5'd19       :      x19      <=       write_data   ;
	5'd20       :      x20      <=       write_data   ;
	5'd21       :      x21      <=       write_data   ;
	5'd22       :      x22      <=       write_data   ;
	5'd23       :      x23      <=       write_data   ;
	5'd24       :      x24      <=       write_data   ;
	5'd25       :      x25      <=       write_data   ;
	5'd26       :      x26      <=       write_data   ;
	5'd27       :      x27      <=       write_data   ;
	5'd28       :      x28      <=       write_data   ;
	5'd29       :      x29      <=       write_data   ;
	5'd30       :      x30      <=       write_data   ;
	5'd31       :      x31      <=       write_data   ;
	endcase                            
	end
	
	always@(*)
	if(!rst_n)
	read_data1 = 32'd0;
	else begin
	case(read_reg1)
	5'd0        :      read_data1      =     x0     ;
	5'd1        :      read_data1      =     x1     ;
	5'd2        :      read_data1      =     x2     ;
	5'd3        :      read_data1      =     x3     ;
	5'd4        :      read_data1      =     x4     ;
	5'd5        :      read_data1      =     x5     ;
	5'd6        :      read_data1      =     x6     ;
	5'd7        :      read_data1      =     x7     ;
	5'd8        :      read_data1      =     x8     ;
	5'd9        :      read_data1      =     x9     ;
	5'd10       :      read_data1      =     x10    ;
	5'd11       :      read_data1      =     x11    ;
	5'd12       :      read_data1      =     x12    ;
	5'd13       :      read_data1      =     x13    ;
	5'd14       :      read_data1      =     x14    ;
	5'd15       :      read_data1      =     x15    ;
	5'd16       :      read_data1      =     x16    ;
	5'd17       :      read_data1      =     x17    ;
	5'd18       :      read_data1      =     x18    ;
	5'd19       :      read_data1      =     x19    ;
	5'd20       :      read_data1      =     x20    ;
	5'd21       :      read_data1      =     x21    ;
	5'd22       :      read_data1      =     x22    ;
	5'd23       :      read_data1      =     x23    ;
	5'd24       :      read_data1      =     x24    ;
	5'd25       :      read_data1