DAC8550 datasheet analysis

I need use stm32 to control DAC8550 and design PCB by myslef. So I write down something important through datasheet.

1.The DAC8550 requires an external reference voltage to set its output range. The DAC8550 incorporates a power-on reset circuit that ensures that the DAC output powers up at midscale and remains there until a valid write takes place to the device.

The input coding to the DAC8550 is 2's complement, so the ideal output voltage is given by

D = decimal equivalent of the 2's complement code that is loaded to the DAC register

D ranges from –32768 to 32767 where D = 0 is centered at VREF / 2.

So it means when power on and before load data to the DAC register, DAC8550 will output VREF / 2. It's necessary to set DAC register in order to output 0V.

By the way, DAC uses Resistor String to control output volatge. It's easy to understand.

2.Pin Functions

VDD is supply power and should be 2.7V to 5.5V

SYNC (synchronous input signal for data frames): effective at low levels. When the SYNC pin is at a low level, it will enable the input shift register to transmit data when the falling edge of the clock signal arrives. DAC updates after the 24th clock (if the SYNC signal is raised before the end of the 24th clock, the write sequence is ignored)

SCLK (Serial Clock Input Signal): Data transmission rate up to 30MHz

Din (Serial Data Input Signal): At each falling edge of the SCLK clock input signal, data (0 or 1) is written to a 24 bit input shift register

3.Power-Down Modes

The DAC8550 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register

When both bits are set to 0, the device works normally with a typical current consumption of 200 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. The advantage with this configuration is that the output impedance of the device is known while in power-down mode. There are three different options. The output is connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (High-Z)

4.Serial Interface

The write sequence begins by bringing the SYNC line LOW. Data from the DIN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the DAC8550 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is excuted (that is, a change in DAC register contents and/or a change in the mode of operation).

At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when the SYNC signal is HIGH than it does when it is LOW, SYNC should be idled LOW between write sequences for lowest power operation of the part. As mentioned above, it must be brought HIGH again just before the next write sequence

The input shift register is 24 bits wide, as shown in Figure below. The first six bits are unused bits. The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). The next 16 bits are the data bits. These bits are transferred to the DAC register on the 24th falling edge of SCLK.

In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure below.