A77 Cache protection behavior&Error injection

Cache protection behavior

The configuration of the RAS extension that is implemented in the Cortex-A77 core includes cache protection.

In this case, the Cortex-A77 core protects against errors that result in a RAM bitcell holding the incorrect value.

The RAMs in the Cortex-A77 core have the following capability:

SED

Single Error Detect. One bit of parity is applicable to the entire word. The word size is specific for each RAM and depends on the protection granule.

Interleaved parity

One bit of parity is applicable to the even bits of the word, and one bit of parity is applicable to the odd bits of the word.

SECDED

Single Error Correct, Double Error Detect.

Table A8-1 Cache protection behavior indicates which protection type is applied to each RAM.

The core can progress and remain functionally correct when there is a single bit error in any RAM.

If there are multiple single bit errors in different RAMs, or within different protection granules within the same RAM, then the core also remains functionally correct.

If there is a double bit error in a single RAM within the same protection granule, then the behavior depends on the RAM:

• For RAMs with SECDED capability, the core detects and either reports or defers the error. If the error is in a cache line containing dirty data, then that data might be lost.
• For RAMs with only SED, the core does not detect a double bit error. This might cause data corruption.

If there are three or more bit errors within the same protection granule, then depending on the RAM and the position of the errors within the RAM, the core might or might not detect the errors.

The cache protection feature of the core has a minimal performance impact when no errors are present.

Table A8-1 Cache protection behavior

RAM	Protection type	Protection granule	Correction behavior
L0 macro-op cache	SED	48 bits	The line that contains the error is invalidated from the macro-op cache and fetched again from the L1 instruction cache.
L1 instruction cache tag	1 parity bit	31 bits	The line that contains the error is invalidated from the L1 instruction cache and fetched again from the subsequent memory system.
L1 instruction cache data	SED	72 bits	The line that contains the error is invalidated from the L1 instruction cache and fetched again from the subsequent memory system.
L1 BTB	None	-	-
L1 GHB	None	-	-
L1 BIM	None	-	-
L1 data cache tag	SECDED	34 bits + 7 bits for ECC attached to the word.	The cache line that contains the error gets evicted, corrected in line, and refilled to the core.
L1 data cache data	SECDED	32 bits of data +1 poison bit + 7 bits for ECC attached to the word.	The cache line that contains the error gets evicted, corrected in line, and refilled to the core.
MMU translation cache	2 interleaved parity bits	71 bits	Entry invalidated, new pagewalk started to refetch it.
MMU replacement policy	None	-	-
MMU biased replacement	None	-	-
L2 cache tag	SECDED	128KB L2 - 7 ECC bits for 38 tag bits 256KB L2 - 7 ECC bits for 37 tag bits 512KB L2 - 7 ECC bits for 36 tag bits	Tag is corrected inline.
L2 cache data	SECDED	8 ECC bits for 64 data bits	Data is corrected inline.
L2 victim	None	-	-

Error injection

The Cortex-A77 core supports fault injection for the purpose of testing fault handling software.

The core is programmable to inject an error for any of the possible error types (corrected error, deferred error, uncontainable error, and recoverable error) on a future memory access. When that access is performed, the core responds as if an error was detected on that access by asserting error interrupts, logging information in the error records, and taking aborts as appropriate for the type of error. Injecting an error will not affect the data in the RAM or the checking process itself. When a real error is detected on an access for which an injected error is programmed, the injected error will not prevent the core from handling the real error. The RAS register might log the injected error or the real error in this case.

To get the error injection to work:

• Program the Error Record Select Register (ERRSELR_EL1) to select Error record 0.
• Program the Error Record Control Register (ERR0CTLR) to enable error detection/recovery and fault detection.
• Program the Error Pseudo Fault Generation Control Register (ERR0PFGCTL) to allow error injection.

Note

Cacheable code must also be executed, which will cause cacheable transactions that can be injected with errors.

The following table describes all the possible types of error that the core can encounter and therefore inject.

Table A8-3 Errors injected in the Cortex-A77 core

Error type	Description
Corrected errors	A corrected error is generated for a single-bit ECC error on L1 data caches and L2 caches, both on data and tag RAMs.
Deferred errors	A deferred error is generated for a double-bit ECC error on L1 data caches and L2 caches, but only on data RAM.
Uncontainable errors	An uncontainable error is generated for a double-bit ECC error on L1 data caches and L2 caches, but only on tag RAM.

The following table describes the registers that handle error injection in the Cortex-A77 core.

Table A8-4 Error injection registers

Register name	Description
ERR0PFGF_EL1	The ERR Pseudo Fault Generation Feature register defines which errors can be injected.
ERR0PFGCTL_EL1	The ERR Pseudo Fault Generation Control register controls the errors that are injected.
ERR0PFGCDN_EL1	The ERR Pseudo Fault Generation Count Down register controls the fault injection timing.

Note

This mechanism simulates the corruption of any RAM but the data is not actually corrupted.

See also:

• ERR0PFGF, Error Pseudo Fault Generation Feature Register.
• ERR0PFGCTL, Error Pseudo Fault Generation Control Register.
• ERR0PFGCDN, Error Pseudo Fault Generation Count Down Register.