9.1 8道digital

• 1. Give two ways of converting a two input NAND gate to an inverter? 

1. ab short circuit
2. a or b connect to 1

• 2. Design a generator, to produce the following sequence:

0 → 1 → 1 → 1 → 2 → 2 → 3 → 4 → 5 → 7 → 9 → 12 → 16 → 21 → 28 → 37 → 0 → 1 → 1 → 1 → 2 → …

x[n-3]+x[n-2]=x[n]

X0<=0;//output

X1<=1;

X2<=1;

Else begin 

X0<=x1;

X1<=x2;

X2<=x0+x1;

回家画电路图，并上墙

• 3. 7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?

0100010->0010001->1001000->0100100->0010010->0001001->1000100->0100010

• 4. Convert D-FF into divide by 2. (not latch) What is the max clock frequency the circuit can handle, given the following information? 

F/2

Tset=6ns Thold=2ns T_pro=10ns

T>=T_logic+Tcq+Tsetup

Told< Tmin_logic+Tcq_logic

T>=10ns+6ns=16ns

F<=1/16 x10^9 HZ

• 5. N number of XNOR gates are connected in series such that the N inputs (A0,A1,A2......) are given in the following way: A0 & A1 to first XNOR gate and A2 & O/P of First XNOR to second XNOR gate and so on..... Nth XNOR gates output is final output. How does this circuit work? Explain in detail? 

11->0, 00->1, 01->0, 10->0

even parity detector

• 6. Using four registers, design a circuit that stores the four values present at an 8-bit input D during the previous four clock cycles. The circuit should have a single 8-bit output that can be configured using two inputs s1 and s0 to output any one of the four registers. (Hint: use an 8-bit 4x1 mux.)

3.19: 4个串联的registers，+mux

• 7.用sv的constraint实现randc功能

Class randc_Test;

rand bit[7:0] data;

bit[7:0] que[$];

constraint rand{ unique{data, que};};

Function void post_randomize(); 

que.push_back(data);

If (sque.size()==2**7) begin

que[$].delete();

End

Endfunction

Endclass

• 8. How to design a memory controller with in-order read responses?

ROB=reorder buffer/fifo

https://chipressco.wpcomstaging.com/2019/08/12/how-to-design-a-memory-controller-with-in-order-read-responses/

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