9.7 8道题

5.墙上review：axi，ahb，apb

6.cdc 单个电平的时钟跨越

Module cdc;

Input data_in;

Output data_out;

Reg data_in_f;

Reg data_in_ff;

always @(posedge clk or negedge rstn) begin

if(!rstn) begin

Data_in_f<=0;

Data_in_ff<=0;

end 

else begin

Data_in_f<=data_in;

Data_in_ff<=data_in_f;

end

end

Assign data_out=data_in_ff;

7.cdc 单个脉冲的时钟跨越（检测toggle）

1.把脉冲信号转化为边沿

2.取边沿电路，把边沿转化为脉冲

always @（posedge clk1 or negedge rstn） 

begin

if（!rstn)

Mux_out<=0;

Else if(data_in) 

Mux_out<=~mux_out;

Else

Mux_out<=mux_out;

End

Always @(posedge clk2 or negedge rstn)

Begin

If(!rstn) begin

Data_f<=0;

Data_ff<=0;

Data_out<=0;

End 

else begin

{Data_out, data_ff, data_f}<={data_ff, data_f, mux_out};

End

End

Assign result_out<=data_ff^data_out;

8.sequencer detector

FSM/shifter registers