DC综合-user guide learning

1.Automatic Ungrouping

The compile_ultra command automatically ungroups logical hierarchies. Ungrouping merges subdesigns of a given level of the hierarchy into the parent cell or design. It removes hierarchical boundaries and allows Design Compiler to improve timing by reducing the levels of logic and to improve area by sharing logic.

You can also manually ungroup hierarchies by using the ungroup command or the set_ungroup command followed by compile_ultra

2.Register Retiming

Register retiming is a sequential optimization technique that moves registers through the combinational logic gates of a design to optimize timing and area. Register retiming adds an opportunity for improving circuit timing.

Design Compiler provides the following ways to perform register retiming:

• The optimize_registers command performs retiming of sequential cells (edgetriggered registers or level-sensitive latches) for pipelined designs. For more information about this retiming strategy, see Pipelined-Logic Retiming.

• The compile_ultra command supports the -retime option, which enables Design Compiler to automatically perform local retiming moves to improve worst negative slack (WNS). This capability, called adaptive retiming, optimizes an entire design. It works best with general non-pipelined logic.

Register retiming is a sequential optimization technique that moves registers through the combinational logic gates of a design to optimize timing and area. Register retiming adds an opportunity for improving circuit timing.

3.Area Optimization

During area optimization, Design Compiler attempts to minimize the number of gates in the design without degrading delay cost.

You can use the optimize_netlist -area command as the final area recovery step at the end of the synthesis flow.