DC综合-user guide learning-优化技术

1.Optimizing Once for Best- and Worst-Case Conditions

You can constrain your design one time for both minimum (best-case) and maximum (worst-case) optimization and timing analysis.

You can constrain the design by using either a single logic library or multiple libraries.

Constraint-Related Commands

set_min_library set_operating_conditions set_wire_load_model set_wire_load_mode set_wire_load_min_block_size set_wire_load_selection_group set_clock_uncertainty

set_clock_transition set_drive set_load set_port_fanout_number set_resistance

2.Optimizing With Multiple Libraries

The set_min_library command directs Design Compiler to use multiple technology libraries for minimum- and maximum-delay analyses in one optimization run.

If a library cell with the same name, the same pins, and the same timing arcs exists in the min_library, Design Compiler uses the timing information from the min_library. If the tool cannot find a matching cell in the min_library, it uses the cell in the max_library.

set_operating_conditions to control and report delay analysis.

3.Preserving Subdesigns

You can preserve a subdesign during optimization by using the set_dont_touch command. The command places the dont_touch attribute on cells, nets, references, and designs in the current design to prevent these objects from being modified or replaced during optimization.

3.1Preserving Cells, References, and Designs

You cannot manually or automatically ungroup objects marked as dont_touch. That is, the ungroup command and the compile -ungroup_all and -auto_ungroup options have no effect on objects marked as dont_touch.

3.2Preserving Nets

The dont_touch attribute is ignored on nets that have unmapped cells on them. During compilation, Design Compiler issues warnings for dont_touch nets connected to unmapped cells (generic logic).

You can preserve specific nets throughout the compilation process by setting the enable_keep_signal_dt_net variable to true before using the set_dont_touch command on the net. When you do this, the dont_touch attribute on the net sets an implicit size_only attribute on logic connected to that net even if logic connected to it is unmapped and not combinational.

3.3Removing a dont_touch Setting

To remove the dont_touch attribute, use the remove_attribute command or the set_dont_touch command set to false.

3.4Preserving the Clock Network After Clock Tree Synthesis

To preserve a clock network after clock tree synthesis, use the set_dont_touch_network command. This command sets a dont_touch_network attribute on a net group. When placed on a clock tree, the dont_touch_network attribute ensures that your clock network is preserved during subsequent optimizations

By default, the propagation stops at output ports, or at sequential components if setup and hold relationships exist. If you use the -no_propagate option, the propagation stops at any logic cell.

The propagation of the dont_touch_network attribute occurs only in a forward direction,The propagation cannot go backward, even to electrically connected nets in the same net group. This method of propagation highlights an important difference between the set_dont_touch_network and the set_ideal_network commands: the set_ideal_network command propagates in both the forward and backward directions.

4.Optimizing Datapaths

Datapath optimization is comprised of two steps: Datapath extraction, which transforms arithmetic operators (for example, addition, subtraction, and multiplication) into datapath blocks, and datapath implementation, which uses a datapath generator to generate the best implementations for these extracted components. Datapath optimization is enabled by default when you use the compile_ultra command.

Datapath optimization provides the following benefits:

• Shares datapath operators

• Extracts the datapath

• Explores better solutions that might involve a different resource-sharing configuration

• Allows the tool to make better tradeoffs between resource sharing and datapath optimization

5.Optimizing Buffer Trees

Design Compiler allows you to build balanced buffer trees to fix design rule violations and improve timing delays caused by high-fanout nets. You can also generate a report for buffer trees and remove buffer trees.

5.1Reporting Buffer Trees

You can generate a report for a buffer tree at the specified driver pins or driver nets by using the report_buffer_tree command.

5.2Removing Buffer Trees

You can remove buffer trees at a specified driver pin, load pin, or driver net on a mapped design by using the clean_buffer_tree command.