增强秒表 basys-3 实现

module CLK_to_clk
#(parameter T1MS = 7500000) 
(
    input CLK,rst,
    output clk
);
    reg [32:0]count;
    always @(posedge CLK,posedge rst)
    begin
        if(rst)
            count<=0;
        else 
        begin 
            if(count < T1MS)
                count<= count+1 ;
            else count <= 0;
        end
    end
    assign clk = (count==T1MS)?1:0;
endmodule

module stopwatch(
    input CLK,rst,
    input go,up, // up信号 =1 则 倒计时
    output reg [3:0]M,D,
    output reg [5:0]SS
    );
    wire clk;
    CLK_to_clk C(CLK,rst,clk);
    reg [3:0]M_next,D_next;
    reg [5:0]SS_next;
always@(posedge CLK,posedge rst)
    begin
        if(rst)
            begin
                M <= 4'b0;
                D <= 4'b0;
                SS <= 6'b0;
            end
        else 
           if(go == 1)
           begin 
             M <= M_next;
             D <= D_next;
             SS <= SS_next;
           end
end



always @(posedge clk,posedge rst)
begin
    if(rst)
        begin
            D_next <= 0;
            SS_next <=0;
            M_next <=0;
        end
    else begin
        if(up==1)
            begin 
                if(D != 9)
                    D_next = D + 1; 
                else 
                    begin
                    D_next = 4'd0;
                    if(SS != 59)
                        SS_next = SS + 1;
                    else
                        begin
                        SS_next = 6'd0;
                        if(M != 9)
                            M_next = M +1;
                        else 
                            M_next = 0;
                        end
                    end
            end
        else
        begin
            if(D != 0)
                D_next = D - 1; 
            else 
            begin
                D_next = 4'd9;
                if(SS != 0)
                    SS_next = SS - 1;
                else
                    begin
                    SS_next = 6'd59;
                    if(M != 0)
                        M_next = M - 1;
                    else 
                        M_next = 4'd9;
                    end
            end
        end
    end
end

endmodule

module display_stopwatch(
    input CLK,rst,
    input [3:0]D,M,
    input [5:0]SS,
    output reg [10:0]display_out,
    output reg point
);
reg [19:0]count=0; 
reg [2:0] sel=0; 
parameter T2MS=1000; 
wire [3:0] digit_h[59:0];
wire [3:0] digit_l[59:0];
wire [6:0] seg_show[9:0];
generate
    genvar i;
    for(i=0;i<60;i=i+1)
    begin: init_SS
        assign digit_l[i] = (i%10) ;//秒的个位
        assign digit_h[i] = (i/10) ;//秒的十位
    end
endgenerate

assign seg_show[0] = 7'b0000001;
assign seg_show[1] = 7'b1001111;
assign seg_show[2] = 7'b0010010;
assign seg_show[3] = 7'b0000110;  
assign seg_show[4] = 7'b1001100;
assign seg_show[5] = 7'b0100100;
assign seg_show[6] = 7'b0100000;
assign seg_show[7] = 7'b0001111;
assign seg_show[8] = 7'b0000000;
assign seg_show[9] = 7'b0000100;


always@(posedge CLK,posedge rst) 
    if(rst)
        display_out <= 11'b0;
    else 
    begin   
         case(sel) 
         0:begin display_out<={4'b0111 , seg_show[M]};  point <= 0;end  // minute
         1:begin display_out<={4'b1011 , seg_show[ digit_h[SS] ]}; point <=1 ;end  // Second_high
         2:begin display_out<={4'b1101 , seg_show[ digit_l[SS] ]}; point<=0;end // second_low
         3:begin display_out<={4'b1110 , seg_show[D]};point<=0; end  // Dsec
         default:display_out<=11'b1111_1111111; 
         endcase 
    end 
    
always@(posedge CLK) 
 begin 
     count<=count+1; 
     if(count==T2MS) 
     begin 
         count<=0; 
         sel<=sel+1; 
         if(sel==3) 
         sel<=0; 
     end 
end

endmodule

module top_stopwatch(
    input CLK,rst,
    input go, up,
    output [10:0]display_out,
    output point
);
    wire [3:0] M,D;
    wire [5:0] SS; 
    stopwatch stp(
        .CLK(CLK),
        .rst(rst),
        .go(go),
        .up(up),
        .M(M),
        .SS(SS),
        .D(D)
    );
    display_stopwatch dis_stp (
        .CLK(CLK),
        .rst(rst),
        .D(D),
        .SS(SS),
        .M(M),
        .display_out(display_out),
        .point(point)
    );
endmodule

约束文件

set_property PACKAGE_PIN W5 [get_ports CLK] 
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
set_property PACKAGE_PIN V17 [get_ports go] 
set_property PACKAGE_PIN V16 [get_ports up] 
set_property PACKAGE_PIN T18 [get_ports rst] 
set_property PACKAGE_PIN V7 [get_ports point] 
set_property IOSTANDARD LVCMOS33 [get_ports point]
set_property IOSTANDARD LVCMOS33 [get_ports go]
set_property IOSTANDARD LVCMOS33 [get_ports up]  
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports CLK] 
set_property PACKAGE_PIN W4 [get_ports {display_out[10]}] 
set_property PACKAGE_PIN V4 [get_ports {display_out[9]}] 
set_property PACKAGE_PIN U4 [get_ports {display_out[8]}] 
set_property PACKAGE_PIN U2 [get_ports {display_out[7]}] 
set_property PACKAGE_PIN W7 [get_ports {display_out[6]}] 
set_property PACKAGE_PIN W6 [get_ports {display_out[5]}] 
set_property PACKAGE_PIN U8 [get_ports {display_out[4]}] 
set_property PACKAGE_PIN V8 [get_ports {display_out[3]}] 
set_property PACKAGE_PIN U5 [get_ports {display_out[2]}] 
set_property PACKAGE_PIN V5 [get_ports {display_out[1]}] 
set_property PACKAGE_PIN U7 [get_ports {display_out[0]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[9]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[8]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[7]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[6]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[5]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[4]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[3]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[1]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[2]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[0]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[10]}]

这个写法不太规范，生成的clk不应该当作时钟用。