第二十二讲 complex_fsm

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module      complex_fsm
(
    input   wire    sys_clk,
    input   wire    sys_rst_n,
    input   wire    pi_money_one,
    input   wire    pi_money_half,

    output   reg    po_money,

    output   reg    po_cola

);

parameter   IDLE    =   5'b0001;
parameter   HALF    =   5'b0001;
parameter   ONE     =   5'b0010; 
parameter   ONE_HALF=   5'b0100;
parameter   TWO     =   5'b1000;

reg         [4:0]       state;
wire        [1:0]       pi_money;


assign pi_money = {pi_money_one,pi_money_half};

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        state <= IDLE;
    else    case(state)
                    IDLE    : if(pi_money == 2'b01)
                                state <= HALF;
                            else if(pi_money == 2'b10)
                                state <= ONE;
                            else
                                state <= IDLE;
                    HALF    : if(pi_money == 2'b01)
                                state <= ONE;
                            else if(pi_money == 2'b10)
                                state <= ONE_HALF;
                            else
                                state <= HALF;
                    ONE     : if(pi_money == 2'b01)
                                state <= ONE_HALF;
                            else if(pi_money == 2'b10)
                                state <= TWO;
                            else
                                state <= ONE; 
                    ONE_HALF: if(pi_money == 2'b01)
                                state <= TWO;
                            else if(pi_money == 2'b10)
                                state <= IDLE;
                            else
                                state <= ONE_HALF; 
                    TWO     : if(pi_money == 2'b01)
                                state <= IDLE;
                            else if(pi_money == 2'b10)
                                state <= IDLE;
                            else
                                state <= TWO;
                    default: state <= IDLE;
                endcase  
        
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        po_cola <= 1'b0;
    else if((state == TWO && pi_money == 2'b01)||(state == TWO&& pi_money == 2'b10)||(state == ONE_HALF && pi_money == 2'b10))
        po_cola <= 1'b1;
    else
        po_cola <= 1'b0;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        po_money <= 1'b0;
    else if(state == TWO && pi_money == 2'b10)
        po_money <= 1'b1;
    else
        po_money <= 1'b0;


          





endmodule

仿真文件一直仿真不出来后来查报错的原因是模块的命名没有改，一定要记得仿真文件的模块名和再软件填写的模块名一样，否则就会和我一样苦逼

`timescale 1ns/1ns
module  tb_complex_fsm();

reg     sys_clk;
reg     sys_rst_n;
reg     pi_money_one;
reg     pi_money_half;
reg     random_data_gen;

wire    po_cola;
wire    po_money;

initial begin
    sys_clk     =   1'b1;
    sys_rst_n  <=   1'b0;
    #20
    sys_rst_n  <=   1'b1;
end

always #10 sys_clk = ~sys_clk;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        random_data_gen <= 1'b0;
    else
        random_data_gen <= {$random} % 2;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        pi_money_one <= 1'b0;
    else 
        pi_money_one <= random_data_gen;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
            pi_money_half <= 1'b0;
        else 
            pi_money_half <= ~random_data_gen;
            //取反是因为一次只能投一个币，即 pi_money_one 和 pi_money_half 不能同时为 1

wire        [4:0]       state = complex_fsm_inst.state;
wire        [1:0]       pi_money = complex_fsm_inst.pi_money;

initial begin
    $timeformat(-9,0,"ns",6);
    $monitor("time %t :pi_money_one=%b pi_money_half=%b pi_money=%b state=%b po_cola=%b po_money=%b",$time,pi_money_one,pi_money_half,pi_money,state,po_cola,po_money);
end

complex_fsm complex_fsm_inst
(
            .sys_clk                (sys_clk),
            .sys_rst_n              (sys_rst_n),
            .pi_money_one           (pi_money_one),
            .pi_money_half          (pi_money_half),

            .po_money               (po_money),
            .po_cola                (po_cola)

);

endmodule