2021-06-11

独热码状态机

一、实验代码
module ex8_1(clock,reset,x,y1,y2) ;
input clock,reset;
input x;
output y1,y2;
reg y1,y2;

reg [3:0] cstate,nstate;

parameter s0=4’b0001,s1=4’b0010,
s2=4’b0100,s3=4’b1000;

always @ (posedge clock or posedge reset)
begin
if (reset)
cstate<=s0;
else
cstate<=nstate;
end

always @ (cstate or x)
begin
case (cstate)
s0:begin
if (x0)
nstate=s1;
else
nstate=s3;
end
s1:begin
if (x0)
nstate=s2;
else
nstate=s0;
end
s2:begin
if (x0)
nstate=s3;
else
nstate=s1;
end
s3:begin
if (x0)
nstate=s0;
else
nstate=s2;
end
default : nstate=s0;
endcase
end

always @ (cstate or x)
begin
case (cstate)
s0 : begin
if (x0)
y1=1;
else
y1=0;
end
s1 : begin
if (x0)
y1=0;
else
y1=0;
end
s2 : begin
if (x0)
y1=0;
else
y1=0;
end
s3 : begin
if (x0)
y1=0;
else
y1=1;
end
default :y1=0;
endcase
end

always @ (cstate or x)
begin
if (cstates0 && x0)
y2=1;
else if (cstates3 && x1)
y2=1;
else
y2=0;
end

endmodule
二、实验过程
1、新建工程
2、新建文件

3、将代码放入编辑框，保存，点击compie all进行代码检验是否有错误，然后点击simulate进行联合仿真

4、实验结果

三、实验视频
https://v.qq.com/x/page/w32523t3te4.html