北邮 数字系统设计 概念题死记硬背就能拿分的部分

死记硬背

本笔记总结了16-22年考卷中全部的概念题及书上可能会考的概念题需要背的部分。

• 下面序号指的是PPT前面的序号（James的ppt部分序号可能会乱，但是大体顺序是不会变的。如果变了学弟学妹们就自己参考即可。要背的内容都是固定的。）

01

What is digital system:

• digits: discrete values, in binary: 0 and 1
• system: process, store and transmit bits

How to represent bits 0 and 1

• Bit 0 is represented by a range of low voltage
• Bit 1 is represented by a range of high voltage

What is the advantage to consider signals as bits?

• The system is more robust due to the noise margin

What happens when you try to transmit a ‘0’ or ‘1’ in a real, non-ideal system *

• there is noise interference, to safeguard the whole system, we need noise margin between inputs and outputs

Gates

02

Why we prefer to use HDL

• Circuit becomes more and more complicated
• Schematic entry is tedious and error-prone
• A HDL model gives better readability and maintenance

How to test a VHDL model using a testbench

• Create simulated inputs in the testbench
• Connect the stimuli to the model as a component
• Simulate the testbench for outpts

解释书写testbench的几个部分的书写方式

The characteristics of the testbench in VHDL

• A VHDL test bench is virtual circuit/system that creates an instance of the top module and generates stimuli to inputs of the instance
• Simulation outputs are recorded and assist verification
• test bench itself is not involved in implementation

03

Hierarchical Design

• The large-scale digital system is broken into pieces called blocks
• Blocks are interconnected to form the circuit

Combinational circuit

• has its outputs at any time determined only by the inputs (has no memory)

Sequential circuit

• contains element that store bits values (has memory)

04

What is the common representation for signed number

• 2’s complement representation

What is the 2’s complement representation

• use the binary value $2^N-A$ to represent negative number

Why 2’s complement

• can keep arithmetic operations consistent for both signs
• （更实在一点的）It eliminates the need of subtraction

Describe briefly an application for Shifter

• Used for Serial to parallel conversion/ Parallel to serial conversion（具体看图）
• Serial input to S and enable the shifting by clearing H（指信号为0）
• Parallel output available at {X, Y}

---

What is overflow

• overflow happens when an operation produces a result outside the range that can be represented by N bits

How to detect an overflow

• (N+1)-th carry differs from N-th carry （最高位的carry与次高位的carry不同）

05

Synchronous System

• behavior/outputs changed at discrete moments in time

Asynchronous System

• change at any instant of time

Define the clock signal

• clock signal is a periodic digital wave of a certain frequency (OR A clock is a periodic signal that alternates between 0 and 1 at a certain frequency)
• A signal shared by all storage elements for Synchronisation - to ensure that each of them to change its output(if any) only at desired moments of changes. We call that clock signal. and it’s usually Periodic

What is positive edge

• moment when the clock changes from 0 to 1

clock signal for a synchronous digital system

• synchronises all element

How to prevent Inferred Latch

• make sure you provide a default signal assignment or a catch-all condition
• create edge-trigger components using 'event

---

What is register

• we group a set of D flip-flops to store a word, it is called a register

---

Two main ways to present a input to a system

• Serial: one bit is presented per cycle
• Parallel: N bits together at a cycle

---

What is a Counter

• Is a circuit that counts in binary, can be view as a simple state machine

What is the function of CLK to counter

• a clock is usually required to govern the rate of counting

---

Effects of delay

• logic gates and flip-flops have some propagation delays

What do u need to do with a Asynchronous Counter (Ripple Counters is asynchronous)

• wait until the output becomes stable to read the correct answer

What is synchronous counters (Counter using HAs is synchronous counter)

• outputs change simutaneously

07

08-10

Define state machines

• clocked synchronous sequential circuit
• state only changes on clock edges
• finite number of states

Moore Machines

• Output given ONLY current state

Mealy Machines

• outputs given BOTH current state and inputs

What does it mean by one hot ecoding of states

• One-hot encoding means $N$ states are encoding as 0…010…0: ($N-1$) zeros and only one ‘1’ in the encoding

What are the advantages of one-hot encoding

• Determining the state has a low and constant cost of accessing one flip-flop
• Changing the state has the constant cost cost of accessing two flip-flops
• Easy to design and modify
• Easy to detect illegal states

10

VHDL

WHEN

不用写在process中

with S select
    Y <= D3 when "11",
    	 D2 when "10",
    	 D1 when "01",
    	 D0 when others;

OUT <= P2 when (F = "11") else
       P2 when (F = "10") else
       P1 when (F = "01") else
       P0 when (F = "00") else '0';

FOR

不用写在process中

FA_MAP_gen: for i in 0 to 3 generate
	INST: FA port map();
end generate FA_MAP_gen;

IF

architecture silly_example of my_ex is
begin
	proc1: process (A, B, C)
	begin
		if (A = '1' and B = '0' and C = '0') then
			F_OUT <= '1';
		elsif (B = '1' and C = '1') then
			F_OUT <= '1';
        else
			F_OUT <= '0';
		end if;
	end process proc1;
end silly_example;

CASE

architecture case_ex of my_ex is
	signal INPUT: std_logic_vector(2 downto 0);
begin
	INPUT <= A & B & C;
	proc1: process (INPUT)
	begin
		case (INPUT) is
			when "100" => F_OUT <= '1';
			when "011" => F_OUT <= '1';
			when "111" => F_OUT <= '1';
			when others => F_OUT <= '0';
		end case;
	end process proc1;
end case_ex;

Decoder

entity decoder_3_8 is
port ( A : in std_logic_vector(2 downto 0);
	   D : out std_logic_vector(7 downto 0));
end decoder_3_8;
architecture decoder_3_8_arch of decoder_3_8 is
begin
	D <= "00000001" when A = "000" else
		 "00000010" when A = "001" else
		 …
		 "01000000" when A = "110" else
		 "10000000";
end decoder_3_8_arch;

With Enable

/: active-low signal

architecture arch of decoder_2_4_en is
begin
    D <= "0001" when A = "00" and nE = '0' else
        "0010" when A = "01" and nE = '0' else
        "0100" when A = "10" and nE = '0' else
        "1000" when A = "11" and nE = '0' else "0000";
end arch;

Encoder

Priority Encoder

architecture arch of pridec_4_2 is
begin
    A <= "11" when D(3) = '1' else
         "10" when D(2) = '1' else
         "01" when D(1) = '1' else 
         "00";
    V <= D(3) or D(2) or D(1) or D(0);
end arch;

MUX

architecture arch_mux4 of mux4 is
begin
	Y <= D(3) when (S = "11") else
	D(2) when (S = "10") else
	D(1) when (S = "01") else
	D(0) when (S = "00") else
	'0';
end arch_mux4;

MUX Expansion

architecture arch of mux16 is
	component mux4 is
	port (D: in std_logic_vector(3 downto 0);
		  S: in std_logic_vector(1 downto 0);
		  Y: out std_logic);
	end component;
	signal X: std_logic_vector(3 downto 0);
begin
	L1_M3: mux4 port map (D(15 downto 12), S(1 downto 0), X(3));
	L1_M2: mux4 port map (D(11 downto 8), S(1 downto 0), X(2));
	L1_M1: mux4 port map (D( 7 downto 4), S(1 downto 0), X(1));
	L1_M0: mux4 port map (D( 3 downto 0), S(1 downto 0), X(0));
	L2_M1: mux4 port map (X, S(3 downto 2), Y);
end arch;

Barrel Shifter

architecture arch of barrel4 is
	component mux2 is
	port (A, B, S: in std_logic; -- Y <= A when S = '0' else B;
		  Y: out std_logic);
	end component;
	signal D1, D0, X1, X0: std_logic_vector(3 downto 0);
begin
	MUX2_GEN: for i in 3 downto 0 generate
	L1: mux2 port map (D0(i), D1(i), shift_n(0), X0(i));
	L2: mux2 port map (X0(i), X1(i), shift_n(1), Y(i));
	end generate MUX2_GEN;
	D0 <= D;
	D1 <= D0(2 downto 0) & '0'; -- shifted bits level 1
	X1 <= X0(1 downto 0) & "00"; -- shifted bits level 2
end arch;

Ripple Adder

只设了一个信号，给两端用，Cout取(4 downto 1)，Cin取(3 downto 0)

• for 中设给每一个component设值
• for 外对Interna Signal的MSB和LSB分别赋值

	signal C: std_logic_vector(4 downto 0);
begin
	FA_map_gen:
	for i in 0 to 3 generate
		INST: FA port map(X=>X(i), Y=>Y(i), CIN=>C(i),S=>S(i), COUT=>C(i+1));
	end generate FA_map_gen;
	C(0) <= CIN;
	COUT <= C(4);
end structural;

D flip-flop

architecture my_d_ff of d_ff is
begin
    dff: process(CLK)
    begin
        if (CLK' event and CLK = '1') then --rising_edge
            Q <= D;
        end if;
    end process;
end my_d_ff;

Loadable Register

entity reg8 is
port ( REG_IN: in std_logic_vector(7 downto 0);
       LD, CLK: in std_logic;
       REG_OUT: out std_logic_vector(7 downto 0));
end reg8;
   
architecture reg8_arch of reg8 is
begin
	reg: process (CLK)
	begin
		if (CLK'event and CLK = '1') then
			if (LD = '1') then
				REG_OUT <= REG_IN;
			end if;
		end if;
	end process reg;
end reg8_arch;

Shift Register with Hold

Hold: active-low

entity ShiftRegHold is
	port (CLK, HOLDn : in std_logic;
		  S_IN : in std_logic;
		  Q : out std_logic_vector(3 downto 0));
end ShiftRegHold;
architecture beh of ShiftRegHold is
	signal S, Qint, D: std_logic_vector(3 downto 0);
begin
	Q <= Qint; -- mirror to output
	reg: process (CLK)
	begin
		if (CLK'event and CLK = '1') then
			Qint <= D;
		end if;
	end process;
	D <= Qint when HOLDn = '0' else S; -- 2-to-1 MUX
	S <= Qint(2 downto 0) & S_IN; -- shifted bits
end beh;

Universal Shift Register

library IEEE;
use IEEE.std_logic_1164.all;

entity UniversalShiftRegister is
port(
	D       : in  std_logic_vector(3 downto 0);
	S       : in  std_logic_vector(1 downto 0);
	CLK,RST : in  std_logic;
	S_IN    : in  std_logic;
	Q       : out std_logic_vector(3 downto 0)
);
end UniversalShiftRegister;

architecture arch of UniversalShiftRegister is
	signal Dint, Qint, Sr, Sl: std_logic_vector(3 downto 0);
begin
	Q <= Qint;
	
	reg:process(CLK, RST)
	begin
		if RST = '1' then
			Qint <= (others => '0');
		else
			if (CLK'event and CLK = '1') then
				Qint <= Dint;
			end if;
		end if;
	end process;
	
	-- the following 'Sr' means shifting right. the direction of 'right' is actully toward MSB side
	-- the following 'Sl' means shifting left. the direction of 'left' is actully toward LSB side
	Dint <= Qint when S = "00" else
			  Sr   when S = "01" else
			  Sl   when S = "10" else D;
   
	Sr <= Qint(2 downto 0) & S_IN;
	Sl <= S_IN & Qint(3 downto 1);
end arch;