数字电路第六次实验

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHECKSEQ IS
PORT(
	CLK,XIN,NRST:IN STD_LOGIC;
	ZOUT:OUT STD_LOGIC
);
END CHECKSEQ;
ARCHITECTURE RTL OF CHECKSEQ IS
TYPE STATE_TYPE IS(S0,S1,S2,S3,S4,S5);
SIGNAL STATE:STATE_TYPE;
BEGIN
	PROCESS(NRST,CLK)
	BEGIN
		IF NRST='1' THEN STATE<=S0;
		ELSIF CLK'EVENT AND CLK='1' THEN 
		CASE STATE IS
		WHEN S0=>IF XIN='1' THEN STATE<=S1;
					ELSE STATE<=S0;
					END IF;
		WHEN S1=>IF XIN='1' THEN STATE<=S2;
					ELSE STATE<=S0;
					END IF;
		WHEN S2=>IF XIN='0' THEN STATE<=S3;
					ELSE STATE<=S2;
					END IF;
		WHEN S3=>IF XIN='1' THEN STATE<=S4;
					ELSE STATE<=S0;
					END IF;
		WHEN S4=>IF XIN='0' THEN STATE<=S5;
					ELSE STATE<=S2;
					END IF;
		WHEN S5=>IF XIN='1' THEN STATE<=S1;
					ELSE STATE<=S0;
					END IF;
		END CASE;
		END IF;
	END PROCESS;
	
	PROCESS(STATE)
	BEGIN
		CASE STATE IS
		WHEN S0 =>ZOUT<='0';
		WHEN S1 =>ZOUT<='0';
		WHEN S2 =>ZOUT<='0';
		WHEN S3 =>ZOUT<='0';
		WHEN S4 =>ZOUT<='0';
		WHEN S5 =>ZOUT<='1';
		END CASE;
	END PROCESS;
END RTL;

---

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY GENSEQ IS
PORT(
	CLK,RST:IN STD_LOGIC;
	YOUT:OUT STD_LOGIC
);
END GENSEQ;

ARCHITECTURE RTL OF GENSEQ IS
TYPE STATE_TYPE IS(SX,S0,S1,S2,S3,S4,S5,S6,S7,S8);
SIGNAL STATE:STATE_TYPE;
BEGIN
PROCESS(CLK,RST)
BEGIN
IF RST='1' THEN STATE<=SX;
ELSIF CLK'EVENT AND CLK='1' THEN 
	CASE STATE IS
	WHEN S0=>STATE<=S1;
	WHEN S1=>STATE<=S2;
	WHEN S2=>STATE<=S3;
	WHEN S3=>STATE<=S4;
	WHEN S4=>STATE<=S5;
	WHEN S5=>STATE<=S6;
	WHEN S6=>STATE<=S7;
	WHEN S7=>STATE<=S8;
	WHEN S8=>STATE<=S0;
	WHEN OTHERS=>STATE<=S0;
	END CASE;
END IF;
END PROCESS;

PROCESS(STATE)
BEGIN
CASE STATE IS
WHEN S0=>YOUT<='0';
WHEN S1=>YOUT<='1';
WHEN S2=>YOUT<='0';
WHEN S3=>YOUT<='1';
WHEN S4=>YOUT<='1';
WHEN S5=>YOUT<='0';
WHEN S6=>YOUT<='1';
WHEN S7=>YOUT<='1';
WHEN S8=>YOUT<='1';
WHEN SX=>YOUT<='0';
END CASE;
END PROCESS;
END RTL;

 说明一下，代码里的状态SX指的是rst有效时的状态，即输出0。这里为什么不直接用S0呢？是因为rst结束以后还需要从第一个bit开始输出，如果用S0表示rst时的状态，则结束后状态会变成S1，与题意不符（即少输出了一个0）。

---

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LEDLIGHT IS
PORT(
	CLK,SEL1,SEL0:IN STD_LOGIC;
	LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END LEDLIGHT;
ARCHITECTURE RTL OF LEDLIGHT IS
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL CNT:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL COUNT1:INTEGER RANGE 0 TO 1;
SIGNAL COUNT2:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
SEL(1)<=SEL1;
SEL(0)<=SEL0;
PROCESS(CLK)
BEGIN 
IF CLK'EVENT AND CLK='1' THEN
CASE SEL IS
WHEN "00" => CNT<="00000000";
WHEN "01" => IF COUNT1=0 THEN CNT<="00000000";COUNT1<=1;
             ELSE CNT<="11111111";COUNT1<=0; 	
             END IF;	
WHEN "10" => COUNT2<=COUNT2+'1';
				CASE COUNT2 IS
				WHEN "000"=>CNT<="10000000";
				WHEN "001"=>CNT<="01000000";
				WHEN "010"=>CNT<="00100000";
				WHEN "011"=>CNT<="00010000";
				WHEN "100"=>CNT<="00001000";
				WHEN "101"=>CNT<="00000100";
				WHEN "110"=>CNT<="00000010";
				WHEN "111"=>CNT<="00000001";
				END CASE;
WHEN OTHERS =>CNT<="11111111";
END CASE;
END IF;
END PROCESS;
LED<=CNT;
END RTL;