计算公式
R = Y + 1.402*(V-128) = Y + 1.402*CR - 1.402*128
G = Y - 0.344*(U-128) - 0.714*(V-128) = Y - 0.344*CB -0.714*CR + 1.058*128
B = Y + 1.772*(U-128) = Y + 1.772*CB - 1.772*128
FPGA实现
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/08/06 20:34:03
// Design Name:
// Module Name: img_ycbcr_rgb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module img_ycbcr_rgb(
input clk ,
input rst ,
input [ 23: 0] img_data_i ,
input valid_i ,
output [ 23: 0] img_data_o