天津大学—数字逻辑第三次作业：硬件描述语言（HDL）基础——过程块

一

module alwaysblock(
    input a, 
    input b,
    output out_assign,
    output out_alwaysblock
);
logic out_alwaysblock;

	// 代码量预计3~4行
    assign out_assign = a && b;
    always_comb begin
           out_alwaysblock= a && b;
      end
endmodule

二

`timescale 1ns/1ns

module alif1(
    input 	a,
    input 	b,
    input 	sel_b1,
    input 	sel_b2,
    output 	out_assign,
    output 	out_alwaysblock   ); 
    
	//预计代码量6-7行
  
    assign out_assign = sel_b1 & sel_b2 ? b : a;
    logic out_alwaysblock;
    always_comb begin
        if (sel_b1 & sel_b2) begin 
            out_alwaysblock = b;
        end
        else begin
            out_alwaysblock = a;
        end
    end
endmodule

三

module alif2(
    input      cpu_overheated,
    input      arrived,
    input      gas_tank_empty,
    output     shut_off_computer,
    output     keep_driving
);

    reg shut_off_computer, keep_driving;  //logic shut_off_computer, keep_driving; (SystemVerilog HDL)

	// 代码量预计3~4行

    always @(*) begin                   // always_comb (SystemVerilog HDL)
        if (cpu_overheated)
           shut_off_computer = 1;
           else shut_off_computer =0;
    end

    always @(*) begin                   // always_comb (SystemVerilog HDL)
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else keep_driving=0;
    end

endmodule

四

module case1(
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output[3:0] out
);
    logic out;
 always_comb begin
case(sel)
    3'b000 : out=data0;
    3'b001 : out=data1;
    3'b010 : out=data2;
    3'b011 : out=data3;
    3'b100 : out=data4;
    3'b101 : out=data5;
default : out=0;
endcase 
 end
	// 代码量预计11行

endmodule

五

module case2(
    input [3 : 0] in,
    output[1 : 0] pos
);

	// 代码量预计20行
    logic pos;
   always_comb begin
    case(in)
    4'b0000: pos = 2'b00;
    4'b0001: pos = 2'b00;
    4'b0010: pos = 2'b01;
    4'b0011: pos = 2'b00;
    4'b0100: pos = 2'b10;
    4'b0101: pos = 2'b00;
    4'b0110: pos = 2'b01;
    4'b0111: pos = 2'b00;
    4'b1000: pos = 2'b11;
    4'b1001: pos = 2'b00;
    4'b1010: pos = 2'b01;
    4'b1011: pos = 2'b00;
    4'b1100: pos = 2'b10;
    4'b1101: pos = 2'b00;
    4'b1110: pos = 2'b01;
    4'b1111: pos = 2'b00;
    default: pos = 2'b00;
    endcase
    end
endmodule

六

module case3(
    input [7 : 0] in,
    output reg [2 : 0] pos
);

	// 代码量预计13行
 always @(*)
 casez (in)
    8'bzzzzzzz1:pos=3'b000;
    8'bzzzzzz10:pos=3'b001;
    8'bzzzzz100:pos=3'b010;
    8'bzzzz1000:pos=3'b011;
    8'bzzz10000:pos=3'b100;
    8'bzz100000:pos=3'b101;
    8'bz1000000:pos=3'b110;
    8'b10000000:pos=3'b111;
     default: pos = 0;
    endcase

endmodule

七

module nolatches(
    input logic [15:0] scancode,
    output logic left,
    output logic down,
    output logic right,
    output logic up  
    ); 

     always_comb begin
        left = 1'b0;
        down = 1'b0;
        right = 1'b0;
        up = 1'b0;
        case(scancode)
            16'he06b:begin
                left = 1'b1;
            end
            16'he072:begin
                down = 1'b1;
            end
            16'he074:begin
                right = 1'b1;
            end
            16'he075:begin
                up = 1'b1;
            end
            default: ;
        endcase
    end
endmodule

八

module popcount255(
    input [254 : 0] in, 
    output[  7 : 0] out
);

	// 代码量预计6~7行
 integer i;
 logic out;
    always@(*)begin
        out = 1'b0;  
        for(i=0;i< 255;i=i+1)begin
            out = out + in[i];  
        end  
    end

endmodule

九

module vector100r(
    input logic [99 : 0] in, 
    output logic [99 : 0] out
);


    integer i;
    always@(*)begin
        for(i=0;i<100;i=i+1)begin
             out[i] = in[99-i];
        end
    end


endmodule

求赞！！！！！