IMX6ULL Linux移植（附下载链接）_imx6ull 改写的linux内核怎么下载-CSDN博客

本文链接：https://blog.csdn.net/weixin_72213026/article/details/139013986

1、linux内核官网下载并解压缩

https://github.com/nxp-imx/linux-imx/archive/refs/heads/lf-6.1.y.zip

2、修改顶层Makefile文件

在linux内核顶层文件linux-imx-lf-6.1.y中的Makefile中添加：

ARCH = arm
CROSS_COMPILE ?= /opt/gcc-aarch32-10.3-2021.07/bin/arm-none-linux-gnueabihf-

其中，CROSS_COMPILE路径为自己的交叉编译器路径。添加结果如下:

3、添加 igkboard_defconfig 文件

imx_v7_defconfig文件是Linux内核源代码中针对i.MX 7系列处理器（基于ARM架构）的默认配置文件。这个文件包含了为i.MX 7系列处理器预先定义的一系列内核配置选项，以便于开发者在编译Linux内核时可以直接使用这些预设的配置，而无需手动设置每个选项。

当使用imx_v7_defconfig文件作为起点来配置Linux内核时，它会为你的应用提供一套合理的默认设置。这些设置包括CPU架构、设备驱动程序、文件系统支持等。当然，你仍然可以根据项目需求对这些配置进行修改和优化。

我用的开发板处理器是NXP i.MX6ULL 系列 Cortex-A7 处理器，在顶层文件直接运行如下指令即可：

cp arch/arm/configs/imx_v7_defconfig arch/arm/configs/igkboard_defconfig

4、添加设备树文件

在arch/arm/boot/dts下，imx6ul-14x14-evk.dtsi文件是一个设备树源文件（Device Tree Source，DTS），用于描述和配置i.MX 6UL处理器在14x14尺寸的评估板（EVK）上的硬件设备信息，它是针对NXP（原Freescale）公司生产的i.MX6UL处理器的一种开发板（Evaluation Kit）的设备树描述文件。

复制imx6ul-14x14-evk.dtsi文件，重命名为igkboard.dts:

cp imx6ul-14x14-evk.dtsi igkboard.dts

参考imx6ul-14x14-evk.dtsi文件修改igkboard.dts，添加自己的设备树文件：

// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.

/dts-v1/;

#include "imx6ull.dtsi"

/ {
        model = "Board Based on i.MX6ULL";      
        compatible = "imx6ull,igkboard", "fsl,imx6ull";

        chosen {
                stdout-path = &uart1;
        };

        memory@80000000 {
                device_type = "memory";
                reg = <0x80000000 0x20000000>;
        };

        reserved-memory {
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;

                linux,cma {
                        compatible = "shared-dma-pool";
                        reusable;
                        size = <0xa000000>;
                        linux,cma-default;
                };
        };

        backlight-display {
                compatible = "pwm-backlight";
                pwms = <&pwm1 0 5000000>;
                brightness-levels = <0 4 8 16 32 64 128 255>;
                default-brightness-level = <6>;
                status = "okay";
        };

        pxp_v4l2 {
                compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
                status = "okay";
        };

        reg_sd1_vmmc: regulator-sd1-vmmc {
                compatible = "regulator-fixed";
                regulator-name = "VSD_3V3";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                off-on-delay-us = <20000>;
                enable-active-high;
        };

        reg_peri_3v3: regulator-peri-3v3 {
                compatible = "regulator-fixed";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_peri_3v3>;
                regulator-name = "VPERI_3V3";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
                /*
                 * If you want to want to make this dynamic please
                 * check schematics and test all affected peripherals:
                 *
                 * - sensors
                 * - ethernet phy
                 * - can
                 * - bluetooth
                 * - wm8960 audio codec
                 * - ov5640 camera
                 */
                regulator-always-on;
        };

        reg_can_3v3: regulator-can-3v3 {
                compatible = "regulator-fixed";
                regulator-name = "can-3v3";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                regulator-boot-on;
                regulator-always-on;
        };

        sound-wm8960 {
                compatible = "fsl,imx-audio-wm8960";
                model = "wm8960-audio";
                audio-cpu = <&sai2>;
                audio-codec = <&codec>;
                audio-asrc = <&asrc>;
                hp-det-gpio = <&gpio5 4 0>;
                audio-routing =
                        "Headphone Jack", "HP_L",
                        "Headphone Jack", "HP_R",
                        "Ext Spk", "SPK_LP",
                        "Ext Spk", "SPK_LN",
                        "Ext Spk", "SPK_RP",
                        "Ext Spk", "SPK_RN",
                        "LINPUT2", "Mic Jack",
                        "LINPUT3", "Mic Jack",
                        "RINPUT1", "AMIC",
                        "RINPUT2", "AMIC",
                        "Mic Jack", "MICB",
                        "AMIC", "MICB";
        };

};

&clks {
        assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
        assigned-clock-rates = <786432000>;
};

&csi {
        status = "disabled";

        port {
                csi1_ep: endpoint {
                        remote-endpoint = <&ov5640_ep>;
                };
        };
};

&i2c2 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";

        codec: wm8960@1a {
                #sound-dai-cells = <0>;
                compatible = "wlf,wm8960";
                reg = <0x1a>;
                wlf,shared-lrclk;
                wlf,hp-cfg = <3 2 3>;
                wlf,gpio-cfg = <1 3>;
                clocks = <&clks IMX6UL_CLK_SAI2>;
                clock-names = "mclk";
        };

        rtc1208 {
                compatible = "isil,isl1208";
                status = "okay";
        };

        ov5640: ov5640@3c {
                compatible = "ovti,ov5640";
                reg = <0x3c>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_csi1 &pinctrl_camera_clock>;
                clocks = <&clks IMX6UL_CLK_CSI>;
                clock-names = "csi_mclk";
                pwn-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
                rst-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
                csi_id = <0>;
                mclk = <24000000>;
                mclk_source = <0>;
                status = "disabled";
                port {
                        ov5640_ep: endpoint {
                                remote-endpoint = <&csi1_ep>;
                        };
                };
        };

};

&fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1>;
        phy-mode = "rmii";
        phy-handle = <&ethphy0>;
        phy-supply = <&reg_peri_3v3>;
        phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
        phy-reset-duration = <50>;
        phy-reset-post-delay = <15>;
        status = "okay";
};

&fec2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2>;
        phy-mode = "rmii";
        phy-handle = <&ethphy1>;
        phy-supply = <&reg_peri_3v3>;
        phy-reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
        phy-reset-duration = <50>;
        phy-reset-post-delay = <15>;
        status = "okay";

        mdio {
                #address-cells = <1>;
                #size-cells = <0>;

                ethphy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-id0022.1560";
                        reg = <0>;
                        micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
                        clock-names = "rmii-ref";

                };

                ethphy1: ethernet-phy@1 {
                        compatible = "ethernet-phy-id0022.1560";
                        reg = <1>;
                        micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
                        clock-names = "rmii-ref";
                };
        };
};

&can1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_flexcan1>;
        xceiver-supply = <&reg_can_3v3>;
        status = "okay";
};

&can2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_flexcan2>;
        xceiver-supply = <&reg_can_3v3>;
        status = "okay";
};

&i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";

        magnetometer@e {
                compatible = "fsl,mag3110";
                reg = <0x0e>;
                vdd-supply = <&reg_peri_3v3>;
                vddio-supply = <&reg_peri_3v3>;
                position = <2>;
        };

        fxls8471@1e {
                compatible = "fsl,fxls8471";
                reg = <0x1e>;
                position = <0>;
                interrupt-parent = <&gpio5>;
                interrupts = <0 8>;
        };
};

&lcdif {
        assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
        assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lcdif_dat
                     &pinctrl_lcdif_ctrl>;
        display = <&display0>;
        status = "okay";

        display0: display@0 {
                bits-per-pixel = <16>;
                bus-width = <16>;

                display-timings {
                        native-mode = <&timing0>;

                        timing0: timing0 {
                                clock-frequency = <30000000>;
                                hactive = <800>;
                                vactive = <480>;
                                hfront-porch = <40>;
                                hback-porch = <88>;
                                hsync-len = <48>;
                                vback-porch = <32>;
                                vfront-porch = <13>;
                                vsync-len = <3>;
                                hsync-active = <0>;
                                vsync-active = <0>;
                                de-active = <1>;
                                pixelclk-active = <0>;
                        };
                };
        };
};

&pwm1 {
        #pwm-cells = <2>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm1>;
        status = "okay";
};

&snvs_poweroff {
        status = "okay";
};

&snvs_pwrkey {
        status = "okay";
};

&sim2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sim2>;
        assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
        assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
        assigned-clock-rates = <240000000>;
        /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control
         * NCN8025:Vcc = ACTIVE_HIGH?5V:3V
         * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V
         */
        pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
        port = <1>;
        sven_low_active;
        status = "okay";
};

&uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
};

&uart2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart2>;
        uart-has-rtscts;
        /* for DTE mode, add below change */
        /* fsl,dte-mode; */
        /* pinctrl-0 = <&pinctrl_uart2dte>; */
        status = "okay";

        bluetooth {
                compatible = "nxp,88w8987-bt";
        };
};

&usbotg1 {
        dr_mode = "otg";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usb_otg1>;
        status = "okay";
};

&usbotg2 {
        dr_mode = "host";
        disable-over-current;
        status = "okay";
};

&usbphy1 {
        fsl,tx-d-cal = <106>;
};

&usbphy2 {
        fsl,tx-d-cal = <106>;
};

&usdhc1 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc1>;
        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
        cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
        keep-power-in-suspend;
        wakeup-source;
        vmmc-supply = <&reg_sd1_vmmc>;
        status = "okay";
};

&usdhc2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc2>;
        pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
        pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
        bus-width = <8>;
        non-removable;
        keep-power-in-suspend;
        wakeup-source;
        status = "okay";
};

&iomuxc {
        pinctrl-names = "default";

        pinctrl_camera_clock: cameraclockgrp {
                fsl,pins = <
                        MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
                >;
        };

        pinctrl_csi1: csi1grp {
                fsl,pins = <
                        MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
                        MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
                        MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
                        MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
                        MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
                        MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
                        MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
                        MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
                        MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
                        MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
                        MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
                >;
        };

        pinctrl_enet1: enet1grp {
                fsl,pins = <
                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
                        MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
                        MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
                        MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
                        MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
                        MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
                        MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x10B0
                >;
        };

        pinctrl_enet2: enet2grp {
                fsl,pins = <
                        MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
                        MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
                        MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x10B0
                >;
        };

        pinctrl_flexcan1: flexcan1grp{
                fsl,pins = <
                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
                >;
        };

        pinctrl_flexcan2: flexcan2grp{
                fsl,pins = <
                        MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
                        MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
                >;
        };

        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
                >;
        };

        pinctrl_i2c2: i2c2grp {
                fsl,pins = <
                        MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
                        MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
                >;
        };

        pinctrl_lcdif_dat: lcdifdatgrp {
                fsl,pins = <
                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
                >;
        };

        pinctrl_lcdif_ctrl: lcdifctrlgrp {
                fsl,pins = <
                        MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
                        /* used for lcd reset */
                        MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
                >;
        };

        pinctrl_qspi: qspigrp {
                fsl,pins = <
                        MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
                        MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
                        MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
                        MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
                        MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
                        MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
                >;
        };

        pinctrl_peri_3v3: peri3v3grp {
                fsl,pins = <
                        MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0
                >;
        };

        pinctrl_pwm1: pwm1grp {
                fsl,pins = <
                        MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
                >;
        };

        pinctrl_sim2: sim2grp {
                fsl,pins = <
                        MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
                        MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
                        MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
                        MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
                        MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
                        MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
                >;
        };

        pinctrl_tsc: tscgrp {
                fsl,pins = <
                        MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
                        MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
                        MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
                >;
        };

        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
                        MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
                >;
        };

        pinctrl_uart2: uart2grp {
                fsl,pins = <
                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
                        MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
                        MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
                >;
        };

        pinctrl_uart2dte: uart2dtegrp {
                fsl,pins = <
                        MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
                        MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
                        MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS  0x1b0b1
                        MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS  0x1b0b1
                >;
        };

        pinctrl_usb_otg1: usbotg1grp {
                fsl,pins = <
                        MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
                >;
        };

        pinctrl_usdhc1: usdhc1grp {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10071
                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
                        MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
                        MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
                        MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
                >;
        };

        pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9

                >;
        };

        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
                fsl,pins = <
                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
                >;
        };

        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
                >;
        };

        pinctrl_usdhc2_8bit: usdhc2grp_8bit {
                fsl,pins = <
                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
                        MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
                        MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
                        MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
                        MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
                >;
        };

        pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
                fsl,pins = <
                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
                        MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
                        MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
                        MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
                        MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
                >;
        };

        pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
                fsl,pins = <
                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
                        MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
                        MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
                        MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
                        MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
                >;
        };

        pinctrl_wdog: wdoggrp {
                fsl,pins = <
                        MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
                >;
        };
};

5、修改arch/arm/boot/dts下的Makefile文件

添加对igkboard-dts文件的编译，修改内容如图所示：

6、编译

    make distclean
    make igkboard_defconfig
    make -j8

编译成功后，可在arch/arm/boot文件夹下找到zImage文件，arch/arm/boot/dts下则有生成的igkboard.dtb文件。