广工电工与电子技术实验报告-篮球竞赛30秒计时器设计

本文链接：https://blog.csdn.net/weixin_74263024/article/details/139452452

实验代码

Basketball_top.v

module Basketball_top (oSEG0, oSEG1, Alarm, nRST, nPAUSE, CLK_50);

input CLK_50;

input nRST;

input nPAUSE;

output Alarm;

output[6:0] oSEG0;

output[6:0] oSEG1;

wire CLK_1Hz;

wire[3:0] TimerH, TimerL;

Divider_50MHz U1 (.CLK_50M(CLK_50), .nCLR(nRST), .CLK_1HzOut(CLK_1Hz));

Basketball U2 (.TimerH(TimerH), .TimerL(TimerL), .Alarm(Alarm), .nRST(nRST), .nPAUSE(nPAUSE), .CP(CLK_1Hz));

SEG7_LUT U3 (.oSEG(oSEG0), .iDIG(TimerL));

SEG7_LUT U4 (.oSEG(oSEG1), .iDIG(TimerH));

endmodule //Basketball_top

Divider_50MHz.v

module Divider_50MHz (CLK_50M, nCLR, CLK_1HzOut);

parameter N=25;

parameter CLK_Freq = 50000000;

parameter OUT_Freq = 1;

input CLK_50M;

input nCLR;

output CLK_1HzOut;

reg CLK_1HzOut;

reg[N-1:0] Count_DIV;

always @(posedge CLK_50M or negedge nCLR) begin

if(! nCLR) begin

CLK_1HzOut <= 0;

Count_DIV <= 0;

end

else begin

if(Count_DIV <= (CLK_Freq/(2*OUT_Freq)-1))

Count_DIV <= Count_DIV + 1'b1;

else begin

Count_DIV <= 0;

CLK_1HzOut <= ~ CLK_1HzOut;

end

end

end

endmodule //Divider_50MHz

Basketball.v

module Basketball (TimerH, TimerL, Alarm, nRST, nPAUSE, CP);

input nRST;

input nPAUSE;

input CP;

output[3:0] TimerH;

output[3:0] TimerL;

reg[3:0] TimerH;

reg[3:0] TimerL;

output Alarm;

assign Alarm = ({TimerH, TimerL} == 8'h00)&(nRST == 1'b1);

always @(posedge CP or negedge nRST or negedge nPAUSE) begin

if(! nRST)

{TimerH, TimerL} <= 8'h30;

else if(! nPAUSE)

{TimerH, TimerL} <= {TimerH, TimerL};

else if({TimerH, TimerL} == 8'h00) begin

{TimerH, TimerL} <= {TimerH, TimerL};

end

else if(TimerL == 4'h0) begin

TimerH <= TimerH - 1'b1;

TimerL <= 4'h9;

end

else begin

TimerH <= TimerH;

TimerL <= TimerL - 1'b1;

end

end

endmodule //Basketball

SEG7_LUT.v

module SEG7_LUT (oSEG, iDIG);

input[3:0] iDIG;

output[6:0] oSEG;

reg[6:0] oSEG;

always @(iDIG) begin

case (iDIG)

4'h1: oSEG = 7'b1111001;

4'h2: oSEG = 7'b0100100;

4'h3: oSEG = 7'b0110000;

4'h4: oSEG = 7'b0011001;

4'h5: oSEG = 7'b0010010;

4'h6: oSEG = 7'b0000010;

4'h7: oSEG = 7'b1111000;

4'h8: oSEG = 7'b0000000;

4'h9: oSEG = 7'b0010000;

4'ha: oSEG = 7'b0001000;

4'hb: oSEG = 7'b0000011;

4'hc: oSEG = 7'b1000110;

4'hd: oSEG = 7'b0100001;

4'he: oSEG = 7'b0000110;

4'hf: oSEG = 7'b0001110;

default: oSEG = 7'b1000000;

endcase

end

endmodule //SEG7_LUT