SOC课程实验——IO端口设计

恍梦.

于 2022-07-09 14:13:14 发布

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分类专栏： SOC 文章标签： fpga开发嵌入式硬件

本文链接：https://blog.csdn.net/wenhaohaohaohao/article/details/125692993

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SOC课程实验

IO端口设计

一、功能分析

1、输入锁存

clk_PO上升沿有效，P0_CS高电平，nP0_IEN低电平，P0_IN->data。

2、输出锁存

clk_PO上升沿有效，P0_CS高电平，nP0_OEN低电平， data->P0_OUT。

二、程序实现

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PC_IO is port(
	clk_P0:in std_logic;
	reset:in std_logic;
	P0_CS:in std_logic;
	P0_IEN:in std_logic;
	P0_OEN:in std_logic;
	InEN:in std_logic;
	OutEN:in std_logic;
	P0_IN:in std_logic_vector (7 downto 0);
	P0_OUT:out std_logic_vector (7 downto 0);
	data_out:out std_logic_vector (7 downto 0);
	data_in:in std_logic_vector (7 downto 0)
	);
end PC_IO;

architecture Behavioral of PC_IO is
begin
process(clk_P0,P0_CS,P0_IEN,P0_IN,P0_OEN)
variable lockin:std_logic_vector(7 downto 0);
begin
     if(reset='1') then
        if(clk_P0' EVENT and clk_P0='1')then
              if( P0_CS='1' and P0_IEN='0') then
                     lockin:=P0_IN;
                     if InEN ='0' then
                        data_out<=lockin;
                     end if;
              end if;
              if( P0_CS='1' and P0_OEN='0') then
                     lockin:=data_in;
                     if OutEN ='0' then
                        P0_OUT<=lockin;
                     end if;
               end if;
	       end if;
	  elsif(reset='0') then
	      P0_OUT<="00000000";
	      data_out <="00000000";
	end if;
end process;
end Behavioral;