半加器
模块图及真值表
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module half_add ( input wire in_1, input wire in_2, output wire sum, output wire count ); assign {count, sum} = in_1 + in_2; endmodule
rtl综合电路
测试文件testbench
`timescale 1ns/1ns module half_add_tb; reg in_1; reg in_2; wire sum; wire count; //模块的实例化 half_add s0 ( .in_1(in_1), .in_2(in_2), .sum(sum), .count(count) ); initial begin #100; in_1 <= 1'b0; in_2 <= 1'b0; #100; in_1 <= 1'b1; in_2 <= 1'b0; #100; in_1 <= 1'b0; in_2 <= 1'b1; #100; in_1 <= 1'b1; in_2 <= 1'b1; #100; $stop; end endmodule
FPGA学习笔记4 -- 加法器的实现
最新推荐文章于 2023-07-02 22:10:19 发布