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vhdl
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whywhatwhenhow
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用vhdl语言实现寄存器
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for ins原创 2009-10-12 14:22:00 · 10427 阅读 · 2 评论 -
vhdl实现寄存器的代码(生成的元件更少)
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for instantiating原创 2009-10-12 17:10:00 · 1470 阅读 · 0 评论 -
并行加法器
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;--并行加法器-- Uncomment the following lines to use the declarations that are-- provided for instanti原创 2009-10-16 15:09:00 · 1208 阅读 · 0 评论 -
使用元件例化的方式以一位全加器构建出四位全加器
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity yiwei is Port ( a : in std_logic; b : in std_logic; cin : in std_l原创 2009-10-18 13:10:00 · 4841 阅读 · 2 评论 -
使用风格1的信号发生器
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for instantiating原创 2009-10-19 14:15:00 · 644 阅读 · 0 评论 -
采用风格2的信号发生器
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for instantiating原创 2009-10-19 20:16:00 · 634 阅读 · 0 评论