library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity yiwei is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
cout: out std_logic;
s : out std_logic);
end yiwei;
architecture Behavioral of yiwei is
begin
s <= a xor b xor cin;
cout <= (a and b) or ((a or b) and cin);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity siwei is
PORT (
m,n : in std_logic_vector (3 downto 0);
r : out std_logic_vector (3 downto 0);
x :in std_logic ;
y :out std_logic
);
end siwei;
architecture jiafaqi of siwei is
component yiwei
Port ( a : in std_logic;
b : in std_logic;