并行加法器

最新推荐文章于 2024-08-23 08:08:19 发布

whywhatwhenhow

最新推荐文章于 2024-08-23 08:08:19 发布

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分类专栏： vhdl 文章标签： vector primitive signal library c

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--并行加法器
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bingxingjiafaqi is
    Port ( a : in std_logic_vector(3 downto 0);
           b : in std_logic_vector(3 downto 0);
           cin : in std_logic;
           s : out std_logic_vector(3 downto 0);
           cout : out std_logic);
end bingxingjiafaqi;

--这个实验中使用信号和变量有什么区别？？？？？？？？？
architecture Behavioral of bingxingjiafaqi is
signal c :std_logic_vector(4 downto 0);
signal d :std_logic_vector(3 downto 0);
signal t :std_logic_vector(3 downto 0);
begin

g1:for i in 0 to 3 generate
  d(i) <= a(i) and b(i);
  t(i) <= a(i) or b(i);
  s(i) <= a(i) xor b(i) xor c(i);
end generate;

c(0) <= cin;
c(1) <= d(0) or (t(0) and c(0));
c(2) <= d(1) or (t(1) and d(0)) or (t(1) and t(0) and c(0));
c(3) <= d(2) or (t(2) and d(1)) or (t(2) and t(1) and d(0)) or (t(2) and t(1) and t(0) and c(0));
c(4) <= d(3) or (t(3) and d(2)) or (t(3) and t(2) and d(1)) or (t(3) and t(2) and t(1) and d(0)) or (t(3) and t(2) and t(1) and t(0) and c(0));
cout <= c(4);

end Behavioral;