Verilog HDL Operators

		Arithmetic Operators  //算术操作符
		Example
		Relational Operators //关系操作符
		Example
		Equality Operators // 等价操作符
		Example
		Logical Operators //逻辑操作符
		Example
		Bit-wise Operators //位操作符
		Example
		Reduction Operators // 规约操作
		Example
		Shift Operators //移位操作
		Example
		Concatenation Operator //连接操作符
		Example
		Replication Operator //赋值操作符
		Example
		Conditional Operators //条件操作符
		Example
		Operator Precedence  //操作符优先级。

the above original link:http://www.asic-world.com/verilog/operators.html