Art of Writing TestBenches（of verilog HDL） Part - IV

		Adding compare Logic //添加比较逻辑
		To make any testbench self checking/automated, first we need to develop a model that mimics the DUT in functionality.  为了是测试基准程序能偶自动校验，我首先要开发一个模型能够反应DuT的功能。 In our example, it's going to be very easy, but at times if the DUT is complex, then to mimic it will be very complex and will require a lot of innovative techniques to make self-checking work.
		1 reg [3:0] count_compare; 2 3 always @ (posedge clk) 4 if (reset == 1'b1) begin 5 count_compare <= 0; 6 end else if ( enable == 1'b1) begin 7 count_compare <= count_compare + 1; 8 end You could download file counter_tb10.v here
		Once we have the logic to mimic the DUT functionality, we need to add the checker logic, which at any given point keeps checking the expected value with the actual value. Whenever there is any error, it prints out the expected and actual value, and also terminates the simulation by triggering the event "terminate_sim".
		1 always @ (posedge clk) 2 if (count_compare ! = count) begin 3 $display ("DUT Error at time %d", $time); 4 $display (" Expected value %d, Got Value %d", count_compare, count); 5 #5 -> terminate_sim; 6 end You could download file counter_tb11.v here
		Now that we have the all the logic in place, we can remove $display and $monitor, as our testbench have become fully automatic, and we don't require to manually verify the DUT input and output. Try changing the count_compare = count_compare +2, and see how compare logic works. This is just another way to see if our testbench is stable.
		We could add some fancy printing as shown in the figure below to make our test environment more friendly.
		C:\Download\work>veridos counter.v counter_tb.v VeriWell for Win32 HDL Sat Jan 18 20:10:35 2003 This is a free version of the VeriWell for Win32 Simulator Distribute this freely; call 1-800-VERIWELL for ordering information See the file "!readme.1st" for more information Copyright (c) 1993-97 Wellspring Solutions, Inc. All rights reserved Memory Available: 0 Entering Phase I... Compiling source file : counter.v Compiling source file : counter_tb.v The size of this model is [5%, 6%] of the capacity of the free version Entering Phase II... Entering Phase III... No errors in compilation Top-level modules: counter_tb ############################################ Applying reset Came out of Reset Terminating simulation Simulation Result : PASSED ########################################### Exiting VeriWell for Win32 at time 96 0 Errors, 0 Warnings, Memory Used: 0 Compile time = 0.0, Load time = 0.0, Simulation time = 0.0 Normal exit Thank you for using VeriWell for Win32
		I know, you would like to see the test bench code that I used to generate the above output, well you can find it here and counter code here.
		There are a lot of things that I have not covered; maybe when I find time, I may add some more details on this subject.
		As to books, I am yet to find a good book on writing test benches.

the original above link : http://www.asic-world.com/verilog/art_testbench_writing4.html