F280049C 输出三相互补对称SPWM波

最新推荐文章于 2022-11-19 09:36:45 发布
最新推荐文章于 2022-11-19 09:36:45 发布
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分类专栏： 基于DSP280049实现电源中算法 文章标签： 单片机 stm32 c语言
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本文链接：https://blog.csdn.net/xht2403267701/article/details/125897485
版权 
/*
 * spwm.c
 *
 *  Created on: 2022年7月17日
 *      Author: EnglishName
 */
#include "F28x_Project.h"
#include "epwm.h"
int tbprd = 1999;
float const table[500] = { 0.5, 0.5063, 0.51259, 0.51888, 0.52517, 0.53146,
                           0.53774, 0.54401, 0.55028, 0.55654, 0.56279, 0.56903,
                           0.57526, 0.58148, 0.58769, 0.59388, 0.60005, 0.60621,
                           0.61236, 0.61848, 0.62459, 0.63068, 0.63674, 0.64279,
                           0.64881, 0.65481, 0.66078, 0.66673, 0.67265, 0.67855,
                           0.68441, 0.69025, 0.69606, 0.70183, 0.70758, 0.71329,
                           0.71897, 0.72461, 0.73021, 0.73579, 0.74132, 0.74681,
                           0.75227, 0.75768, 0.76306, 0.76839, 0.77368, 0.77893,
                           0.78413, 0.78929, 0.7944, 0.79947, 0.80448, 0.80945,
                           0.81437, 0.81925, 0.82407, 0.82883, 0.83355, 0.83821,
                           0.84282, 0.84738, 0.85188, 0.85632, 0.86071, 0.86504,
                           0.86932, 0.87353, 0.87769, 0.88178, 0.88582, 0.88979,
                           0.8937, 0.89755, 0.90134, 0.90506, 0.90872, 0.91232,
                           0.91584, 0.91931, 0.9227, 0.92603, 0.92929, 0.93249,
                           0.93561, 0.93867, 0.94165, 0.94457, 0.94742, 0.95019,
                           0.95289, 0.95553, 0.95809, 0.96057, 0.96299, 0.96533,
                           0.96759, 0.96979, 0.9719, 0.97395, 0.97592, 0.97781,
                           0.97963, 0.98137, 0.98303, 0.98462, 0.98613, 0.98756,
                           0.98892, 0.9902, 0.9914, 0.99252, 0.99357, 0.99454,
                           0.99543, 0.99624, 0.99697, 0.99762, 0.9982, 0.99869,
                           0.99911, 0.99944, 0.9997, 0.99988, 0.99998, 1,
                           0.99994, 0.9998, 0.99958, 0.99928, 0.99891, 0.99845,
                           0.99792, 0.9973, 0.99661, 0.99584, 0.99499, 0.99406,
                           0.99306, 0.99197, 0.99081, 0.98957, 0.98825, 0.98686,
                           0.98538, 0.98383, 0.98221, 0.98051, 0.97873, 0.97687,
                           0.97494, 0.97294, 0.97085, 0.9687, 0.96647, 0.96417,
                           0.96179, 0.95934, 0.95682, 0.95422, 0.95155, 0.94881,
                           0.946, 0.94312, 0.94017, 0.93715, 0.93406, 0.9309,
                           0.92767, 0.92438, 0.92101, 0.91758, 0.91409, 0.91053,
                           0.9069, 0.90321, 0.89945, 0.89564, 0.89176, 0.88781,
                           0.88381, 0.87974, 0.87562, 0.87143, 0.86719, 0.86289,
                           0.85853, 0.85411, 0.84964, 0.84511, 0.84053, 0.83589,
                           0.8312, 0.82646, 0.82166, 0.81682, 0.81192, 0.80698,
                           0.80198, 0.79694, 0.79185, 0.78672, 0.78154, 0.77631,
                           0.77104, 0.76573, 0.76038, 0.75498, 0.74955, 0.74407,
                           0.73856, 0.733, 0.72742, 0.72179, 0.71613, 0.71044,
                           0.70471, 0.69895, 0.69316, 0.68734, 0.68148, 0.6756,
                           0.66969, 0.66376, 0.6578, 0.65181, 0.6458, 0.63977,
                           0.63371, 0.62763, 0.62154, 0.61542, 0.60929, 0.60313,
                           0.59697, 0.59078, 0.58458, 0.57837, 0.57215, 0.56591,
                           0.55967, 0.55341, 0.54715, 0.54088, 0.5346, 0.52832,
                           0.52203, 0.51574, 0.50944, 0.50315, 0.49685, 0.49056,
                           0.48426, 0.47797, 0.47168, 0.4654, 0.45912, 0.45285,
                           0.44659, 0.44033, 0.43409, 0.42785, 0.42163, 0.41542,
                           0.40922, 0.40303, 0.39687, 0.39071, 0.38458, 0.37846,
                           0.37237, 0.36629, 0.36023, 0.3542, 0.34819, 0.3422,
                           0.33624, 0.33031, 0.3244, 0.31852, 0.31266, 0.30684,
                           0.30105, 0.29529, 0.28956, 0.28387, 0.27821, 0.27258,
                           0.267, 0.26144, 0.25593, 0.25045, 0.24502, 0.23962,
                           0.23427, 0.22896, 0.22369, 0.21846, 0.21328, 0.20815,
                           0.20306, 0.19802, 0.19302, 0.18808, 0.18318, 0.17834,
                           0.17354, 0.1688, 0.16411, 0.15947, 0.15489, 0.15036,
                           0.14589, 0.14147, 0.13711, 0.13281, 0.12857, 0.12438,
                           0.12026, 0.11619, 0.11219, 0.10824, 0.10436, 0.10055,
                           0.096791, 0.0931, 0.089473, 0.085912, 0.082416,
                           0.078987, 0.075624, 0.072329, 0.069101, 0.065942,
                           0.062851, 0.05983, 0.056879, 0.053998, 0.051187,
                           0.048448, 0.04578, 0.043185, 0.040661, 0.038211,
                           0.035834, 0.03353, 0.031301, 0.029145, 0.027064,
                           0.025059, 0.023128, 0.021274, 0.019495, 0.017792,
                           0.016166, 0.014616, 0.013144, 0.011748, 0.01043,
                           0.0091897, 0.0080272, 0.0069426, 0.0059362,
                           0.0050082, 0.0041586, 0.0033876, 0.0026954, 0.002082,
                           0.0015475, 0.0010921, 0.00071577, 0.00041861,
                           0.00020065, 6.1931e-05, 2.4773e-06, 2.2296e-05,
                           0.00012138, 0.00029972, 0.00055729, 0.00089404,
                           0.0013099, 0.0018049, 0.0023788, 0.0030316,
                           0.0037632, 0.0045735, 0.0054624, 0.0064296,
                           0.0074751, 0.0085987, 0.0098002, 0.011079, 0.012436,
                           0.01387, 0.015381, 0.016969, 0.018634, 0.020375,
                           0.022192, 0.024084, 0.026052, 0.028095, 0.030214,
                           0.032406, 0.034673, 0.037013, 0.039427, 0.041914,
                           0.044473, 0.047105, 0.049809, 0.052584, 0.055429,
                           0.058346, 0.061332, 0.064388, 0.067513, 0.070706,
                           0.073968, 0.077297, 0.080693, 0.084156, 0.087684,
                           0.091278, 0.094937, 0.09866, 0.10245, 0.1063,
                           0.11021, 0.11418, 0.11822, 0.12231, 0.12647, 0.13068,
                           0.13496, 0.13929, 0.14368, 0.14812, 0.15262, 0.15718,
                           0.16179, 0.16645, 0.17117, 0.17593, 0.18075, 0.18563,
                           0.19055, 0.19552, 0.20053, 0.2056, 0.21071, 0.21587,
                           0.22107, 0.22632, 0.23161, 0.23694, 0.24232, 0.24773,
                           0.25319, 0.25868, 0.26421, 0.26979, 0.27539, 0.28103,
                           0.28671, 0.29242, 0.29817, 0.30394, 0.30975, 0.31559,
                           0.32145, 0.32735, 0.33327, 0.33922, 0.34519, 0.35119,
                           0.35721, 0.36326, 0.36932, 0.37541, 0.38152, 0.38764,
                           0.39379, 0.39995, 0.40612, 0.41231, 0.41852, 0.42474,
                           0.43097, 0.43721, 0.44346, 0.44972, 0.45599, 0.46226,
                           0.46854, 0.47483, 0.48112, 0.48741, 0.4937, 0.5 };
void Init_SPWM(int tbprd)
{
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;

    Init_EPWM1(tbprd); // a SPWM f=100MHz/(1+tbprd)/2=100MHz/(1+1999)/2=25KHz
    Init_EPWM2(tbprd); // b SPWM
    Init_EPWM3(tbprd); // c SPWM// Sync source ePWM1 settings

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;
}
void Init_EPWM1(Uint16 tbprd)
{
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // disable TB clock
    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; // start EPWM1 clock
    EDIS;

    Init_EPWM1GPIO(); // configure epwm1 gpios

    EALLOW;
    PieVectTable.EPWM1_INT = &epwm1_ISR; // interrupt vector
    EDIS;

    IER |= M_INT3;
    PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
    EINT;
    ERTM;

    // TB
    EPwm1Regs.TBCTL.bit.SYNCOSEL = 3; //
    EPwm1Regs.TBCTL2.bit.SYNCOSELX = 0; // disable EPWMxSYNCO sync signal
    EPwm1Regs.TBCTL.bit.PHSEN = 0; // 0: do not load the TBCTR from the TBPHS
    EPwm1Regs.TBPHS.bit.TBPHS = 0;
    EPwm1Regs.TBCTR = 0x0000; // initial value of counter
    EPwm1Regs.TBPRD = tbprd; // time-base counter
    EPwm1Regs.TBCTL.bit.CTRMODE = 2; // 2:up-down-count mode
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // pre-scale divide 2*HSPCLKDIV
    EPwm1Regs.TBCTL.bit.CLKDIV = 0; // pre-scale divide 2^CLKDIV

    // CC
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // 0-shadow enabled; 1-shadow disable
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0; // same as above
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // 0-TBCTR=0时，加载影子寄存器的值到active寄存器           ;if not in shadow mode, no use
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // same as above

    EPwm1Regs.CMPA.bit.CMPA = 0.5 * tbprd;
    EPwm1Regs.CMPB.bit.CMPB = 0.5 * tbprd;

    // AQ
//    EPwm1Regs.AQCTLA.bit.ZRO = 1; // when TBCTR=0, 0-nothing, 1-clear, 2-set, 3-toggle
    EPwm1Regs.AQCTLA.bit.CAU = 2; // when TBCTR=CMPA in up-count mode, 0-nothing, 1-clear, 2-set, 3-toggle
    EPwm1Regs.AQCTLA.bit.CAD = 1;
//    EPwm1Regs.AQCTLB.bit.ZRO = 2; // same as above
//    EPwm1Regs.AQCTLB.bit.CBU = 1; // same as above

    // ET
    EPwm1Regs.ETSEL.bit.INTSEL = 1; // when TBCTR=0, trigger event
    EPwm1Regs.ETSEL.bit.INTEN = 1; // 0-disable interrupt; 1-enable interrupt
    EPwm1Regs.ETPS.bit.INTPRD = 1; // 0-interrupt disabled, 1-one event trigger an interrupt, 2-two event; 3-three event

    // DB  结合DB的图来理解寄存器的配置
    EPwm1Regs.DBCTL.bit.IN_MODE = 0; // epwmxA作为延时驶入源
    EPwm1Regs.DBCTL.bit.DEDB_MODE = 0; // 使能双边沿延时
    EPwm1Regs.DBCTL.bit.POLSEL = 1; // epwmxA,epwmxB翻转一个
    EPwm1Regs.DBCTL.bit.OUT_MODE = 3; // 使能双边沿延时
    EPwm1Regs.DBRED.bit.DBRED = 100; // rising edge delay  1/100e6*100=1us
    EPwm1Regs.DBFED.bit.DBFED = 100; // falling edge delay
    EPwm1Regs.DBCTL.bit.OUTSWAP = 0; // 输出通道交换

//    EALLOW;
//    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // start TB clock
//    EDIS;
}
void EPWM1A_SetCompare(Uint16 val)
{
    EPwm1Regs.CMPA.bit.CMPA = val;
}
void EPWM1B_SetCompare(Uint16 val)
{
    EPwm1Regs.CMPB.bit.CMPB = val;
}
void Init_EPWM1GPIO()
{
    EALLOW;

    GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // enable pull-up
    GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // enable pull-up

    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // configure GPIO00 as EPWM1A
    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // configure GPIO01 as EPWM1B

    EDIS;
}

//EPWM2
void Init_EPWM2(Uint16 tbprd)
{
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // disable TB clock
    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; // start EPWM1 clock
    EDIS;

    Init_EPWM2GPIO(); // configure epwm1 gpios

//    EALLOW;
//    PieVectTable.EPWM2_INT = &epwm2_ISR; // interrupt vector
//    EDIS;
//
//    IER |= M_INT3;
//    PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
//    EINT;
//    ERTM;

    // TB
    EPwm2Regs.TBCTL.bit.SYNCOSEL = 3; //
    EPwm2Regs.TBCTL2.bit.SYNCOSELX = 0; // disable EPWMxSYNCO sync signal
    EPwm2Regs.TBCTL.bit.PHSEN = 0; // 0: do not load the TBCTR from the TBPHS
    EPwm2Regs.TBPHS.bit.TBPHS = 0;
    EPwm2Regs.TBCTR = 0x0000; // initial value of counter
    EPwm2Regs.TBPRD = tbprd; // time-base counter
    EPwm2Regs.TBCTL.bit.CTRMODE = 2; // 2:up-down-count mode
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // pre-scale divide 2*HSPCLKDIV
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // pre-scale divide 2^CLKDIV

    // CC
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = 1; // shadow enabled
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = 1; // same as above
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // if not in shadow mode, no use
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // same as above

    EPwm2Regs.CMPA.bit.CMPA = 0.5 * tbprd; //
    EPwm2Regs.CMPB.bit.CMPB = 0.5 * tbprd;

    // AQ
//    EPwm2Regs.AQCTLA.bit.ZRO = 1; // when TBCTR=0, 0-nothing, 1-clear, 2-set, 3-toggle
    EPwm2Regs.AQCTLA.bit.CAU = 2; // when TBCTR=CMPA in up-count mode, 0-nothing, 1-clear, 2-set, 3-toggle
    EPwm2Regs.AQCTLA.bit.CAD = 1;
//    EPwm2Regs.AQCTLB.bit.ZRO = 2; // same as above
//    EPwm2Regs.AQCTLB.bit.CBU = 1; // same as above

    // ET
    EPwm2Regs.ETSEL.bit.INTSEL = 1; // when TBCTR=0, trigger event
    EPwm2Regs.ETSEL.bit.INTEN = 1; // 0-disable interrupt; 1-enable interrupt
    EPwm2Regs.ETPS.bit.INTPRD = 1; // 0-interrupt disabled, 1-one event trigger an interrupt, 2-two event; 3-three event

    // DB  结合DB的图来理解寄存器的配置
    EPwm2Regs.DBCTL.bit.OUT_MODE = 3; // 使能双边沿延时
    EPwm2Regs.DBCTL.bit.POLSEL = 1; //
    EPwm2Regs.DBCTL.bit.IN_MODE = 0;
    EPwm2Regs.DBRED.bit.DBRED = 100; //100ns
    EPwm2Regs.DBFED.bit.DBFED = 100;

//    EALLOW;
//    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // start TB clock
//    EDIS;
}
void EPWM2A_SetCompare(Uint16 val)
{
    EPwm2Regs.CMPA.bit.CMPA = val;
}
void EPWM2B_SetCompare(Uint16 val)
{
    EPwm2Regs.CMPB.bit.CMPB = val;
}
void Init_EPWM2GPIO()
{
    EALLOW;

    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // enable pull-up
    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // enable pull-up

    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // configure GPIO00 as EPWM1A
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // configure GPIO01 as EPWM1B

    EDIS;
}

// EPWM3
void Init_EPWM3(Uint16 tbprd)
{
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // disable TB clock
    CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; // start EPWM1 clock
    EDIS;

    Init_EPWM3GPIO(); // configure epwm1 gpios

//    EALLOW;
//    PieVectTable.EPWM3_INT = &epwm3_ISR; // interrupt vector
//    EDIS;
//
//    IER |= M_INT3;
//    PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
//    EINT;
//    ERTM;

    // TB
    EPwm3Regs.TBCTL.bit.SYNCOSEL = 3; //
    EPwm3Regs.TBCTL2.bit.SYNCOSELX = 0; // disable EPWMxSYNCO sync signal
    EPwm3Regs.TBCTL.bit.PHSEN = 0; // 0: do not load the TBCTR from the TBPHS
    EPwm3Regs.TBPHS.bit.TBPHS = 0;
    EPwm3Regs.TBCTR = 0x0000; // initial value of counter
    EPwm3Regs.TBPRD = tbprd; // time-base counter
    EPwm3Regs.TBCTL.bit.CTRMODE = 2; // 2:up-down-count mode
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; // pre-scale divide 2*HSPCLKDIV
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // pre-scale divide 2^CLKDIV

    // CC
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = 1; // shadow enabled
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = 1; // same as above
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // if not in shadow mode, no use
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // same as above

    EPwm3Regs.CMPA.bit.CMPA = 0.5 * tbprd; //
    EPwm3Regs.CMPB.bit.CMPB = 0;

    // AQ
//    EPwm3Regs.AQCTLA.bit.ZRO = 1; // when TBCTR=0, 0-nothing, 1-clear, 2-set, 3-toggle
    EPwm3Regs.AQCTLA.bit.CAU = 2; // when TBCTR=CMPA in up-count mode, 0-nothing, 1-clear, 2-set, 3-toggle
    EPwm3Regs.AQCTLA.bit.CAD = 1; // whne TBCTR=CMPA in down count mode, 0-nothing, 1-clear, 2-set, 3-toggle
//    EPwm3Regs.AQCTLB.bit.ZRO = 2; // same as above
//    EPwm3Regs.AQCTLB.bit.CBU = 1; // same as above

    // ET
    EPwm3Regs.ETSEL.bit.INTSEL = 1; // when TBCTR=0, trigger event
    EPwm3Regs.ETSEL.bit.INTEN = 1; // 0-disable interrupt; 1-enable interrupt
    EPwm3Regs.ETPS.bit.INTPRD = 1; // 0-interrupt disabled, 1-one event trigger an interrupt, 2-two event; 3-three event

    // DB  结合DB的图来理解寄存器的配置
    EPwm3Regs.DBCTL.bit.OUT_MODE = 3; // 使能双边沿延时
    EPwm3Regs.DBCTL.bit.POLSEL = 1; //
    EPwm3Regs.DBCTL.bit.IN_MODE = 0;
    EPwm3Regs.DBRED.bit.DBRED = 100;
    EPwm3Regs.DBFED.bit.DBFED = 100;

//    EALLOW;
//    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // start TB clock
//    EDIS;
}
void EPWM3A_SetCompare(Uint16 val)
{
    EPwm3Regs.CMPA.bit.CMPA = val;
}
void EPWM3B_SetCompare(Uint16 val)
{
    EPwm3Regs.CMPB.bit.CMPB = val;
}
void Init_EPWM3GPIO()
{
    EALLOW;

    GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // enable pull-up
    GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // enable pull-up

    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // configure GPIO00 as EPWM1A
    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // configure GPIO01 as EPWM1B

    EDIS;
}
__interrupt void epwm1_ISR(void)
{
    if (sin_index1 >= 500)
        sin_index1 = 0;
    if (sin_index2 >= 500)
        sin_index2 = 0;
    if (sin_index3 >= 500)
        sin_index3 = 0;
    EPwm1Regs.CMPA.bit.CMPA = (int) (tbprd * Modulat * table[sin_index1]);
    EPwm2Regs.CMPA.bit.CMPA = (int) (tbprd * Modulat * table[sin_index2]);
    EPwm3Regs.CMPA.bit.CMPA = (int) (tbprd * Modulat * table[sin_index3]);
    sin_index1++;
    sin_index2++;
    sin_index3++;

    EPwm1Regs.ETCLR.bit.INT = 1; // Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

在中断中查表更新每相的CMPA，实现正弦调制波

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专用SPWM芯片EG8030在三相逆变中的使用
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