韦东山uboot_内核_根文件系统学习笔记1.3.1--第001课_U-boot分析与使用_第003节_u-boot分析之start.s文件学习

根据上一节对于uboot程序的主makefile的分析，我们知道uboot程序首先要执行u-boot-1.1.6\cpu\arm920t\start.s文件，那么本节首先分析该文件。（参考资料https://blog.csdn.net/davidsky11/article/details/25162575）

第一部分：

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */
#define GSTATUS2       (0x560000B4)
#define GSTATUS3       (0x560000B8)
#define GSTATUS4       (0x560000BC)

#define REFRESH        (0x48000024)
#define MISCCR         (0x56000080)

#define LOCKTIME	0x4C000000	/* R/W, PLL lock time count register */
#define MPLLCON		0x4C000004	/* R/W, MPLL configuration register */
#define UPLLCON		0x4C000008	/* R/W, UPLL configuration register */
#define CLKCON		0x4C00000C	/* R/W, Clock generator control reg. */
#define CLKSLOW		0x4C000010	/* R/W, Slow clock control register */
#define CLKDIVN		0x4C000014	/* R/W, Clock divider control */

/*
  globl就是相当于C语言中的Extern，声明此变量，并且告诉链接器此变量是全局的，外部可以访问
  指定入口为_start
  u-boot.lds里面定义了ENTRY(_start),即指定入口为_start 
 */
.globl _start
/* 跳转到reset,这里的代码地址是00000010 */
_start:	b       reset
/*
  ARM是RISC结构，数据从内存到CPU之间的移动只能通过L/S指令来完成，也就是ldr/str指令。
  比如想把数据从内存中某处读取到寄存器中，只能使用ldr
  将_undefined_instruction这个地址处的word(一字节)定义的值赋给pc。

  ARM体系结构规定在上电复位的起始位置必须有8条连续的跳转指令，
  通过硬件来实现。它们就是异常向量表。ARM在上电复位后是从0x0开始启动，
  如果bootloader存在，则是从_start开始执行上面的跳转没有执行。
  设置异常向量表的作用是识别bootloader，以后每当系统有异常出现时，
  cpu会根据异常号从内存0x0处开始查找并做相应的处理   
  下面8条即设置异常中断向量表
 */
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq
/*
当有异常出现ARM会自动执行以下步骤：

1 将下一条指令的地址存放在连接寄存器LR(通常是R14).---保存位置

2 将相应的CPSR(当前程序状态寄存器)复制到SPSR(备份的程序状态寄存器)中

3 根据异常类型，强制设置CPSR运行模式位

4 强制PC从相应异常向量地址取出下一条指令执行，从而跳转到异常处理函数中执行

以_undefined_instruction为例，就是，此处分配了一个word=32bit=4字节的地址空间，里面存放的值是undefined_instruction。
而此处_undefined_instruction也就是该地址空间的地址了。用C语言来表达就是：
_undefined_instruction = &undefined_instruction
或
*_undefined_instruction = undefined_instruction

在后面的代码，我们可以看到，undefined_instruction也是一个标号，即一个地址值，对应着就是在发生“未定义指令”的时候，系统所要去执行的代码。
 */
_undefined_instruction:	.word undefined_instruction //“未定义指令”的时候，系统所要去执行的代码。
_software_interrupt:	.word software_interrupt//软件中断
_prefetch_abort:	.word prefetch_abort//预取指错误
_data_abort:		.word data_abort//数据错误
_not_used:		.word not_used//未定义
_irq:			.word irq//（普通）中断
_fiq:			.word fiq//快速中断
/* 接下来的代码，都要16字节对齐，不足之处，用0xdeadbeef填充 */
	.balignl 16,0xdeadbeef

 第二部分

/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */
//此处和上面的类似，_TEXT_BASE是一个标号地址，此地址中是一个word类型的变量，变量名是TEXT_BASE,此值见名知意，是text的base，即代码的基地址，可以在
//
//u-boot-1.1.6\board\100ask24x0\config.mk
//
//中找到其定义：
//
//TEXT_BASE = 0x33F80000
_TEXT_BASE:
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
	.word __bss_start

.globl _bss_end
_bss_end:
	.word _end

.globl FREE_RAM_END
FREE_RAM_END:
	.word	0x0badc0de

.globl FREE_RAM_SIZE
FREE_RAM_SIZE:
	.word	0x0badc0de

.globl PreLoadedONRAM
PreLoadedONRAM:
	.word	0

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/*第一部分一上来就是跳转到这里*/
/*
 * the actual reset code
 */

reset:
/* 首先进入SVC管理模式，为什么要进行SVC管理模式而不是其它模式，主要因为SVC模式比其他模式有更多的硬件访问权限，并且多了影子寄存器，可以访问的硬件资源更多，详情：http://www.360doc.com/content/13/0514/11/7245213_285318786.shtml */
	/*
	 * set the cpu to SVC32 mode
	 */

/*
 * MRS{条件} 通用寄存器，程序状态寄存器（CPSR或SPSR）
 * mrs :程序状态寄存器访问指令
 * 通用寄存器  程序状态寄存器（CPSR或SPSR）
 * 读取CPSR程序状态寄存器，保存到R0中
 */
	mrs	r0,cpsr
/*
 * bic :BIC{条件}{S} 目的寄存器，操作数1，操作数2,
 * BIC指令用于清除操作数1的某些位，并把结果放置到目的寄存器中。操作数1应是一个寄存器
 * 操作数2可以是一个寄存器，被移位的寄存器，或一个立即数。操作数2为32位的掩码，如果在掩码中设置了某一
 * 位，则清除这一位。未设置的掩码位保持不变。
 * 0x1f=00011111，相当于清除低5位,刚好是模式位。
 */ 
	bic	r0,r0,#0x1f
/*
 * ORR{条件}{S} 目的寄存器，操作数1，操作数2
 * ORR指令用于在两个操作数上进行逻辑或运算，并把结果放置到目的寄存器中。操作数1应是一个寄存器，操作数
 * 2可以是一个寄存器，被移位的寄存器，或一个立即数。该指令常用于设置操作数1的某些位。
 * 0xd3=11010011
 * 将r0与0xd3算数或运算，然后将结果给r0,即把r0的bit[7:6]和bit[4]和bit[2:0]置为1。
 */ 
	orr	r0,r0,#0xd3
/*
 * MSR{条件} 程序状态寄存器（CPSR或SPSR）_<域>，操作数
 * MSR指令用于将操作数的内容传送到程序状态寄存器的特定域中
 * 将r0中的值赋给状态寄存器cpsr
 */
	msr	cpsr,r0

/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
# define pWTCON		0x15300000
# define INTMSK		0x14400008	/* Interupt-Controller base addresses */
# define CLKDIVN	0x14800014	/* clock divisor register */
#elif defined(CONFIG_S3C2410)
# define pWTCON		0x53000000
# define INTMOD     0X4A000004
# define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
# define INTSUBMSK	0x4A00001C
# define CLKDIVN	0x4C000014	/* clock divisor register */
#endif

#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
    /*关闭看门狗
    */
	ldr     r0, =pWTCON
	mov     r1, #0x0
	str     r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov	r1, #0xffffffff
	ldr	r0, =INTMSK
	str	r1, [r0]
    # if defined(CONFIG_S3C2410)
	    ldr	r1, =0x3ff
	    ldr	r0, =INTSUBMSK
	    str	r1, [r0]
    # endif

    #if 0
	    /* FCLK:HCLK:PCLK = 1:2:4 */
	    /* default FCLK is 120 MHz ! */
	    ldr	r0, =CLKDIVN
	    mov	r1, #3
	    str	r1, [r0]
    #endif
#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 */

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    #if 0
		/* 这些代码会使用SP,在NAND启动时会破坏片内内存的部分代码
         * 导致NAND启动时无法使用休眠-唤醒功能
         */
		/* 设置SP指向片内内存 */
		ldr sp, =4092
		ldr r0, =0x12345678
		str r0, [sp]
		ldr r1, [sp]
		cmp r0, r1
		ldrne sp, =0x40000000+4096
		bl clock_init
    #else
	/* 设置时钟, 使用汇编 */
        #define S3C2440_MPLL_400MHZ     ((0x5c<<12)|(0x01<<4)|(0x01))
        #define S3C2440_UPLL_48MHZ      ((0x38<<12)|(0x02<<4)|(0x02))
        #define S3C2440_CLKDIV          (0x05) // | (1<<3))    /* FCLK:HCLK:PCLK = 1:4:8, UCLK = UPLL/2 */

	    ldr r1, =CLKDIVN
	    mov r2, #S3C2440_CLKDIV
	    str r2, [r1]

	    mrc p15, 0, r1, c1, c0, 0		// read ctrl register 
	    orr r1, r1, #0xc0000000 		// Asynchronous	
	    mcr p15, 0, r1, c1, c0, 0		// write ctrl register

        ldr r0,=LOCKTIME
        ldr r1,=0xffffff
        str r1,[r0]
        // delay
        mov     r0, #0x200
    1:  subs    r0, r0, #1
        bne     1b

        // Configure MPLL
        ldr r0,=MPLLCON          
        ldr r1,=S3C2440_MPLL_400MHZ
        str r1,[r0]
        // delay
        mov     r0, #0x200
    1:  subs    r0, r0, #1
        bne     1b

        //Configure UPLL
        ldr     r0, =UPLLCON          
        ldr     r1, =S3C2440_UPLL_48MHZ
        str     r1, [r0]
        // delay
        mov     r0, #0x200
    1:  subs    r0, r0, #1
        bne     1b


    #endif
#endif    

	/* 2. 根据 GSTATUS2[1]判断是复位还是唤醒 */	
	ldr r0, =GSTATUS2
	ldr r1, [r0]
	tst r1, #(1<<1)  /* r1 & (1<<1) */
	bne wake_up	

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
	/*
	 * 如果_start!=_TEXT_BASE
	 * 表明此时是从nand启动，则执行cpu_init_crit
     * 若使用了仿真器直接加载程序的话，程序会下载到SDRAM中
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	adr	r0, _start		/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
	cmp     r0, r1                  /* don't reloc during debug         */
	blne	cpu_init_crit
#endif

	/* Set up the stack						    */
stack_setup:
	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */

#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate:				/* relocate U-Boot to RAM	    */
	adr	r0, _start		/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
	cmp     r0, r1                  /* don't reloc during debug         */
	beq     clear_bss
	
	ldr	r2, _armboot_start
	ldr	r3, _bss_start
	sub	r2, r3, r2		/* r2 <- size of armboot            */
#if 1
	bl  CopyCode2Ram	/* r0: source, r1: dest, r2: size */
#else
	add	r2, r0, r2		/* r2 <- source end address         */

copy_loop:
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end addreee [r2]    */
	ble	copy_loop
#endif
#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */

clear_bss:
	ldr	r0, _bss_start		/* find start of bss segment        */
	ldr	r1, _bss_end		/* stop here                        */
	mov 	r2, #0x00000000		/* clear                            */

clbss_l:str	r2, [r0]		/* clear loop...                    */
	add	r0, r0, #4
	cmp	r0, r1
	ble	clbss_l

SetLoadFlag:
	/* Set a global flag, PreLoadedONRAM */
	adr	r0, _start		/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
	cmp     r0, r1                  /* don't reloc during debug         */
	ldr r2, =PreLoadedONRAM
	mov r3, #1
	streq r3, [r2]

#if 0
	/* try doing this stuff after the relocation */
	ldr     r0, =pWTCON
	mov     r1, #0x0
	str     r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov	r1, #0xffffffff
	ldr	r0, =INTMR
	str	r1, [r0]

	/* FCLK:HCLK:PCLK = 1:2:4 */
	/* default FCLK is 120 MHz ! */
	ldr	r0, =CLKDIVN
	mov	r1, #3
	str	r1, [r0]
	/* END stuff after relocation */
#endif

	ldr	pc, _start_armboot

_start_armboot:	.word start_armboot

/* 1. 按下按键 */
wake_up:
	str r1, [r0]  /* clear GSTATUS2 */
	/* 3. 设置 MISCCR[19:17]=000b, 以释放SDRAM信号 */
	ldr r0, =MISCCR
	ldr r1, [r0]
	bic r1, r1, #(7<<17)
	str r1, [r0]
		
	/* 4. 配置s3c2440的memory controller */
	bl	cpu_init_crit
	
	/* 5. 等待SDRAM退出self-refresh mode */
	mov r0, #1000
1:	subs r0, r0, #1
	cmp r0, #0
	bne 1b
	
	/* 6. 根据GSTATUS[3:4]的值来运行休眠前的函数 */
	ldr r0, =GSTATUS3
	ldr r1, [r0]
	mov pc, r1
	

第三部分

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
     * lowlevel_init函数位置u-boot-1.1.6\board\100ask24x0\lowlevel_init.S
	 */
	mov	ip, lr
	bl	lowlevel_init
	mov	lr, ip
	mov	pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

第四部分

/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	ldr	r2, _armboot_start
	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
	ldmia	r2, {r2 - r3}			@ get pc, cpsr
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add     r8, sp, #S_PC
	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
	str     lr, [r8, #0]                    @ Save calling PC
	mrs     r6, spsr
	str     r6, [r8, #4]                    @ Save CPSR
	str     r0, [r8, #8]                    @ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, _armboot_start		@ setup our mode stack
	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str     lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl 	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl 	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl 	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl 	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl 	do_not_used

@ thisway.diy, 2006.06.24
.globl Launch
    .align	4
Launch:    
    mov r7, r0
    @ diable interrupt
	@ disable watch dog timer
	mov	r1, #0x53000000
	mov	r2, #0x0
	str	r2, [r1]

    ldr r1,=INTMSK
    ldr r2,=0xffffffff  @ all interrupt disable
    str r2,[r1]

    ldr r1,=INTSUBMSK
    ldr r2,=0x7ff       @ all sub interrupt disable
    str r2,[r1]

    ldr     r1, = INTMOD
    mov r2, #0x0        @ set all interrupt as IRQ (not FIQ)
    str     r2, [r1]

    @ 
	mov	ip, #0
	mcr	p15, 0, ip, c13, c0, 0      @	/* zero PID */
	mcr	p15, 0, ip, c7, c7, 0       @	/* invalidate I,D caches */
	mcr	p15, 0, ip, c7, c10, 4      @	/* drain write buffer */
	mcr	p15, 0, ip, c8, c7, 0       @	/* invalidate I,D TLBs */
	mrc	p15, 0, ip, c1, c0, 0       @	/* get control register */
	bic	ip, ip, #0x0001             @	/* disable MMU */
	mcr	p15, 0, ip, c1, c0, 0       @	/* write control register */

    @ MMU_EnableICache
    @mrc p15,0,r1,c1,c0,0
    @orr r1,r1,#(1<<12)
    @mcr p15,0,r1,c1,c0,0

    @ clear SDRAM: the end of free mem(has wince on it now) to the end of SDRAM
    ldr     r3, FREE_RAM_END
    ldr     r4, =PHYS_SDRAM_1+PHYS_SDRAM_1_SIZE    @ must clear all the memory unused to zero
    mov     r5, #0

    ldr     r1, _armboot_start
    ldr     r2, =On_Steppingstone
    sub     r2, r2, r1
    mov     pc, r2
On_Steppingstone:
2:  stmia   r3!, {r5}
    cmp     r3, r4
    bne     2b

    @ set sp = 0 on sys mode
    mov sp, #0

    @ add by thisway.diy 2006.06.26, switch to SVC mode
	msr	cpsr_c,	#0xdf	@ set the I-bit = 1, diable the IRQ interrupt
	msr	cpsr_c,	#0xd3	@ set the I-bit = 1, diable the IRQ interrupt
    ldr sp, =0x31ff5800	
    
    nop
	nop
    nop
	nop

	mov     pc, r7  @ Jump to PhysicalAddress
	nop
    mov pc, lr

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
/* add by www.100ask.net to use IRQ for USB and DMA */
	sub	lr, lr, #4			        @ the return address
	ldr	sp, IRQ_STACK_START	        @ the stack for irq
	stmdb	sp!, 	{ r0-r12,lr }	@ save registers
	
	ldr	lr,	=int_return		        @ set the return addr
	ldr	pc, =IRQ_Handle		        @ call the isr
int_return:
	ldmia	sp!, 	{ r0-r12,pc }^	@ return from interrupt

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl 	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl 	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl 	do_fiq

#endif