BIOS 优化选项说明

Enable = 1, Disable = 0
1、XPT prefetch
 optimize value： 1

 Description：

Xtended Prediciton Table (XPT) Prefetch (Default = Enabled):
This option configures the processor Xtended Prediciton Table (XPT) prefetch feature. The XPT prefetcher exists on top of other prefetchers that that can prefetch data in the core DCU, MLC, and LLC. The XPT prefetcher will issue a speculative DRAM read request in parallel to an LLC lookup. This prefetch bypasses the LLC, saving latency. In some cases, setting this option to disabled can improve performance. In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance. This option must be enabled when Sub-NUMA Clustering is enabled. Values for this BIOS option can be:
• Enabled: Allows a read request sent to the LLC to speculatively issue a copy of the read to the memory controller requesting the prefetch.
• Disabled: Does not allow the LLC to speculatively issue copies of reads. Disabling this will also disables Sub-NUMA Cluster (SNC).

2、LLC dead line
 optimize value： 0

 Description：

LLC Dead Line Allocation
In some Intel CPU caching schemes, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead.” This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled.
Values for this BIOS option can be:
Disabled: Disabling this option can save space in the LLC by never filling MLC dead lines into the LLC.
Enabled: Opportunistically fill MLC dead lines in LLC, if space is available.

3、Patrol Scrub
 optimize value： 0

 Description：

Memory Patrol Scrub (轮训检查)
This BIOS option allows the enabling/disabling of Memory Periodic Patrol Scrubber. The Memory Periodic Patrol Scrubber corrects memory soft errors so that, over the length of the system runtime, the risk of producing multi-bit and uncorrectable errors is reduced.

4、Execute Disable Bit
 optimize value： 0

 Description：

Execute Disable Bit是一个基于硬件的安全特性，可以减少对病毒和恶意代码的攻击，并防止有害软件在服务器或网络上执行和传播。通过构建内置Intel Execute Disable Bit的系统，帮助保护客户的业务资产，并减少与病毒相关的昂贵修复需求。

https://www.cnblogs.com/zqwang0929/p/3358699.html

5、LLC Prefetch
 optimize value： 0

 Description：

Last Level Cache (LLC) Prefetch
This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.
Values for this BIOS option can be:
Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.
Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.
。

6、Enhanced Halt State (C1E)
 optimize value： 0

 Description：

Minimum Processor Idle Power Core C-State (Default = C6 State):
This option can only be configured if the Workload Profile is set to Custom, or this option is not a dependent value for the Workload Profile. This feature selects the processor’s lowest idle power state (C-state) that the operating system uses. The higher the C-state, the lower the power usage of that idle state (C6 is the lowest power idle state supported by the processor). Values for this setting can be:
• C6 State: While in C6, the core PLLs are turned off, the core caches are flushed and the core state is saved to the Last Level Cache. Power Gates are used to reduce power consumption to close to zero. C6 is considered an inactive core.
• C1E State: C1E is defined as the enhanced halt state. While in C1E no instructions are being executed. C1E considered an active core.
• No C-states: No C-states is defined as C0, which is defined as the active state. While in C0, instructions are being executed by the core.

7、SNC
 optimize value： ASM = 0 , SVM =1

 Description：

AUTO supports 1-cluster or 2-clusters depending on IMC interleave. SNC and IMC interleave both AUTO will support 1-cluster (XPT/KTI Prefetch enable) 2-IMC way interleave. SNC Enable supports Full SNC (2 clusters) and 1-way IMC interleave.

Sub NUMA Cluster（SNC）
SNC breaks up the last level cache (LLC) into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC and memory. SNC is a replacement for the cluster on die (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA (Non Uniform Memory Access) domains.
SNC AUTO supports 1-cluster or 2-clusters depending on IMC interleave. SNC and IMC interleave both AUTO will support 1-cluster 2-way IMC interleave.
SNC Enable supports Full SNC (2 clusters) and 1-way IMC interleave. Utilizes LLC capacity more efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.
SNC disable supports 1-cluster and 2-way IMC interleave, the LLC is treated as one cluster.

8、Hyper-Threading
 optimize value： 1

 Description：

启用超线程(启用/禁用逻辑处理器线程的软件方法)。
https://blog.csdn.net/u012278016/article/details/90755338

9、IMC Interleaving
 optimize value： 0

 Description：

IMC (Integrated memory controller) Interleaving
This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs), Memory could be interleaved across sockets, memory controllers, DDR channels, Ranks. Memory is interleaved for performance and thermal distribution.
If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs.
If IMC Interleaving is set to 1-way, there will be no interleaving.
If IMC Interleaving is set to auto, it depends on the SNC (Sub NUMA Clustering) setting, when SNC is set to enbaled, the IMC Interleaving will be 1-way interleave, SNC is set to disabled, the IMC Interleaving will be 2-way interleave.
If SNC is disabled, IMC Interleaving should be set to 2-way. If SNC is enabled, IMC Interleaving should be set to 1-way.

参考资料：
https://www.spec.org/cpu2017/flags/Huawei-Platform-Settings-SKL-V1.7.html
https://www.spec.org/cpu2006/flags/HPE-Platform-Flags-Intel-V1.2-SKX-revB.html