Embedded Systems Architecture programming and design--Chapter 2 Processor and Memory Orgnisation Summary

A summary of the important points in this chapter is given below.

• An embedded system hardware designer must select  an appropriate processor,appropriate set of memories for the system and design an appropriate interfacing circuit between the processor, memories and IO devices.This is done after taking into account the various available processors, stuctural units and architecture, memeory types, sizes and speeds, bus signals and timing diagrams.
• Structural units of  a processor that interconnects through a bus are memory address and data registers, system and arithmetic unit registers, control unit, instruction decoder, instruction registers and arithmetic and logical unit. Registers in processor register sets are important and are meant for various functions during processing .
• Advanced processors have the following additional structural units: prefetch control unit, instruction queuing unit, caches for instruction , data and branch transfer, floating point registers and floating point  arithmetic unit. Pipelining and superscalar features and caches in the processors are used in high performance systems. MIPS or MFLOPS or Dhrystone per second define the computing performance. The goal is to provide the potimal computing performance at the least  cost and least power dissipation and total energy requrement.
• There is a set of instructions and various addressing modes for the arithmetic and  logical instructions, data transfer instructions , I/O instructions and program-flow control instructions. The format of instructions and data and the addressing modes differ in the CISC and RISC processors. Each processor circuit supports a unique instruction set.
• The CISC processor supports a number of addressing modes in its instructions. It gives improved programming features. A programmer uses the multiple types of instructions for the multiple types of data structures. There are variable cycles of execution for an instructions.
• The RISC processor supports only a few addressing modes in tis instructions and gives improved processor performance and single cycle execution per instruction . RISC architecture, superscalar processing ,pipelining, and cache units in advanced processors improve the processor performance an provide faster program execution.
• Share data problem arises when various functions or tasks share a common variable. Atomic operations solve the share data problem. Certain processors have an atomic operations control unit.
• Processor selection can be done using a design table .
• A  system needs ROM and RAM memory of various types and sizes. Various forms of ROM are masked ROM, PROM, EPROM, EEPROM, flash and boot back flash. Basics detailsof the memories are the addresses available ,speed for the read and write poerations and modes of memory access.
• The memory has the blocks of addresses for the program segments, data, stacks, and array addresses. Memories also hold vector addresses(pointers), boot up program instruction set, instruction sets for the tasks, interrupt service routines and functions . Stacks are also at the memory . The designer designs a memory allocation map (and also an IO allocation map in 80x86 case). The size of the memory should be adequate to hold all the codes, data, data sets and structures and stacks.
• Memory access speed should match witch processor structure and access needs.
• A DMA controller should be used to improve system performance by providing direct accesses to the I/O devices and peripherals.
• According to the memory map with I/O device addresses, a locator program is designed to locate the linked object code file and generate table.
• Memory selection can be done by using a design table.
• Each IO device has a distinct set of addresses. Each IO device also has a distingct set of device registers--Data registers, Control Registers and Status registers.  At a device address, there may be more than one register. The device addresses are according the system hardware.
• Bus signals interface the processor , memory and devices. The interface circuit takes into account the timing diagram in reference to processor clock output. The circuit uses the processor control, address and data bus signals and takes into account the timing diagram for the bus signals. A PAL, GAL or FPGA  based circuit provides a single chip solution for the latches, decoders, multiplexers, demultiplexers and any other neccessary interfacing circuit.