用七段数码管显示十六进制数! 共阳极

用七段数码管显示十六进制数!
共阳极

底层文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECL7S IS
PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE ONE OF DECL7S IS
BEGIN
PROCESS(A) BEGIN
CASE A IS
WHEN"0000"=>LED7S<=“1000000”; --0
WHEN"0001"=>LED7S<=“1111001”; --1
WHEN"0010"=>LED7S<=“0100100”; --2
WHEN"0011"=>LED7S<=“0110000”; --3
WHEN"0100"=>LED7S<=“0011001”; --4
WHEN"0101"=>LED7S<=“0010010”; --5
WHEN"0110"=>LED7S<=“0000010”; --6
WHEN"0111"=>LED7S<=“1111000”;–7
WHEN"1000"=>LED7S<=“0000000”; --8
WHEN"1001"=>LED7S<=“0010000”;–9
WHEN"1010"=>LED7S<=“0001000”; --A
WHEN"1011"=>LED7S<=“0000011” ;–b
WHEN"1100"=>LED7S<=“1000110” ;–C
WHEN"1101"=>LED7S<=“0100001” ;–d
WHEN"1110"=>LED7S<=“0000110”; --E
WHEN"1111"=>LED7S<=“0001110”; --null
END CASE;
END PROCESS;
END;

顶层例化
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECL7S_TOP IS
PORT(SW :IN STD_LOGIC_VECTOR(15 DOWNTO 0);
LEDR:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
HEX0:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX2:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX3:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END;
ARCHITECTURE ONE OF DECL7S_TOP IS
COMPONENT DECL7S IS
PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
BEGIN
LEDR<=SW;
U1:DECL7S PORT MAP ( A=>SW(3 DOWNTO 0),LED7S=>HEX0);
U2:DECL7S PORT MAP ( A=>SW(7 DOWNTO 4),LED7S=>HEX1);
U3:DECL7S PORT MAP ( A=>SW(11 DOWNTO 8),LED7S=>HEX2);
U4:DECL7S PORT MAP ( A=>SW(15 DOWNTO 12),LED7S=>HEX3);
END;