tiny4412移植U-Boot 2020.07

$ wget https://xkwy2018.cn/tiny4412/u-boot/2020.07-tiny4412/u-boot-2020.07.tar.bz2
--2020-07-25 10:16:44--  https://xkwy2018.cn/tiny4412/u-boot/2020.07-tiny4412/u-boot-2020.07.tar.bz2
Resolving xkwy2018.cn (xkwy2018.cn)... 64.64.240.120
Connecting to xkwy2018.cn (xkwy2018.cn)|64.64.240.120|:443... connected.
HTTP request sent, awaiting response... 200 OK
Length: 15338841 (15M) [application/x-bzip2]
Saving to: ‘u-boot-2020.07.tar.bz2’

u-boot-2020.07.tar.bz2           100%[=========================================================>]  14.63M  7.10MB/s    in 2.1s    

2020-07-25 10:16:47 (7.10 MB/s) - ‘u-boot-2020.07.tar.bz2’ saved [15338841/15338841]

2.2 解压源码包，并进入源码目录

$ tar xf u-boot-2020.07.tar.bz2
$ cd u-boot-2020.07/

2.3 修改代码

完整的patch文件：https://xkwy2018.cn/tiny4412/u-boot/2020.07-tiny4412/u-boot-2020.07-tiny4412.patch

2.3.0 懒人必备：所有patch一键打补丁

使用curl下载patch文件，然后用patch命令给官方原始u-boot-2020.07打补丁。

$ curl -s https://xkwy2018.cn/tiny4412/u-boot/2020.07-tiny4412/u-boot-2020.07-tiny4412.patch | patch -p1 
patching file arch/arm/dts/Makefile
patching file arch/arm/dts/exynos4412-tiny4412.dts
patching file arch/arm/mach-exynos/Kconfig
patching file arch/arm/mach-exynos/clock_init_exynos4.c
patching file arch/arm/mach-exynos/dmc_init_exynos4.c
patching file arch/arm/mach-exynos/exynos4412_setup.h
patching file arch/arm/mach-exynos/lowlevel_init.c
patching file arch/arm/mach-exynos/tzpc.c
patching file board/samsung/tiny4412/Kconfig
patching file board/samsung/tiny4412/MAINTAINERS
patching file board/samsung/tiny4412/Makefile
patching file board/samsung/tiny4412/tiny4412.c
patching file board/samsung/tiny4412/tools/mktiny4412spl.c
patching file configs/tiny4412_defconfig
patching file include/configs/tiny4412.h

注：如果做了此步骤，2.3后面的章节可全部略过，直接跳到3 配置、编译、下载、测试。

2.3.1 arch/arm/dts/Makefile

在CONFIG_EXYNOS4下面添加tiny4412用的设备树dtb文件

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 89fa448818..107f933f05 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 	exynos4210-smdkv310.dtb \
 	exynos4210-universal_c210.dtb \
 	exynos4210-trats.dtb \
+	exynos4412-tiny4412.dtb \
 	exynos4412-trats2.dtb \
 	exynos4412-odroid.dtb

2.3.2 arch/arm/dts/exynos4412-tiny4412.dts

新增设备树文件：exynos4412-tiny4412.dts

主要是配置调试串口位于UART0，mmc0映射为内置eMMC，mmc2映射为外部SD卡

diff --git a/arch/arm/dts/exynos4412-tiny4412.dts b/arch/arm/dts/exynos4412-tiny4412.dts
new file mode 100755
index 0000000000..8e36148f5c
--- /dev/null
+++ b/arch/arm/dts/exynos4412-tiny4412.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * xkwy's Exynos4412 based Tiny4412 board device tree source
+ *
+ * Copyright (c) xkwy2018.cn
+ *		http://xkwy2018.cn/tiny4412
+ */
+
+/dts-v1/;
+#include "exynos4412.dtsi"
+
+/ {
+	model = "xkwy Tiny4412 based on Exynos4412";
+	compatible = "xkwy,tiny4412", "samsung,exynos4412";
+
+	aliases {
+		console = &serial_0;
+
+		serial0 = &serial_0;
+		serial1 = &serail_1;
+		serial2 = &serial_2;
+		serial3 = &serial_3;
+		serial4 = &serial_4;
+
+		mmc0 = &mshc_0;
+		mmc2 = &sdhci2;
+	};
+};
+
+&serial_0 {
+	status = "okay";
+};
+
+&mshc_0 {
+	samsung,bus-width = <8>;
+	samsung,timing = <2 1 0>;
+	samsung,removable = <0>;
+	fifoth_val = <0x203f0040>;
+	bus_hz = <400000000>;
+	div = <0x3>;
+	index = <4>;
+	status = "okay";
+};
+
+&sdhci2 {
+	samsung,bus-width = <4>;
+	samsung,timing = <1 2 3>;
+	cd-gpios = <&gpk2 2 0>;
+	cd-inverted;
+	status = "okay";
+};

2.3.3 arch/arm/mach-exynos/Kconfig

配置Kconfig，增加TINY4412开发板

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 14347e7c7d..8cf46654c9 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -67,6 +67,10 @@ config TARGET_ORIGEN
 	bool "Exynos4412 Origen board"
 	select SUPPORT_SPL
 
+config TARGET_TINY4412
+	bool "Exynos4412 Tiny4412 board"
+	select SUPPORT_SPL
+
 config TARGET_TRATS2
 	bool "Exynos4412 Trat2 board"
 
@@ -161,6 +165,7 @@ source "board/samsung/smdkv310/Kconfig"
 source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"
 source "board/samsung/origen/Kconfig"
+source "board/samsung/tiny4412/Kconfig"
 source "board/samsung/trats2/Kconfig"
 source "board/samsung/odroid/Kconfig"
 source "board/samsung/arndale/Kconfig"

2.3.4 arch/arm/mach-exynos/clock_init_exynos4.c

修改时钟配置，原来的时钟结构体struct exynos4_clock是Exynos 4210的，Exynos 4412的这一部分寄存器有变化，因此需要改成struct exynos4x12_clock；

再增加一个emmc启动的时钟配置函数emmc_boot_clk_div_set，SPL里面emmc启动时会调用这个函数，由于所有的时钟都已经预先配置好了，因此这个函数里面什么都不做。

diff --git a/arch/arm/mach-exynos/clock_init_exynos4.c b/arch/arm/mach-exynos/clock_init_exynos4.c
index 584e4bac09..7e12d742b0 100644
--- a/arch/arm/mach-exynos/clock_init_exynos4.c
+++ b/arch/arm/mach-exynos/clock_init_exynos4.c
@@ -30,7 +30,11 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/clock.h>
 #include "common_setup.h"
+#if IS_ENABLED(CONFIG_TINY4412)
+#include "exynos4412_setup.h"
+#else
 #include "exynos4_setup.h"
+#endif
 
 /*
  * system_clock_init: Initialize core clock and bus clock.
@@ -38,8 +42,13 @@
  */
 void system_clock_init(void)
 {
+#if IS_ENABLED(CONFIG_TINY4412)
+	struct exynos4x12_clock *clk =
+			(struct exynos4x12_clock *)samsung_get_base_clock();
+#else
 	struct exynos4_clock *clk =
 			(struct exynos4_clock *)samsung_get_base_clock();
+#endif
 
 	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
 
@@ -55,7 +64,11 @@ void system_clock_init(void)
 	writel(CLK_SRC_CAM_VAL, &clk->src_cam);
 	writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
 	writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
+	#if IS_ENABLED(CONFIG_TINY4412)
+	writel(CLK_SRC_LCD_VAL, &clk->src_lcd);
+	#else
 	writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
+	#endif
 
 	sdelay(0x10000);
 
@@ -73,7 +86,11 @@ void system_clock_init(void)
 	writel(CLK_DIV_CAM_VAL, &clk->div_cam);
 	writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
 	writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
+	#if IS_ENABLED(CONFIG_TINY4412)
+	writel(CLK_DIV_LCD_VAL, &clk->div_lcd);
+	#else
 	writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
+	#endif
 
 	/* Set PLL locktime */
 	writel(PLL_LOCKTIME, &clk->apll_lock);
@@ -92,3 +109,8 @@ void system_clock_init(void)
 
 	sdelay(0x30000);
 }
+
+__weak void emmc_boot_clk_div_set(void)
+{
+    ;
+}

2.3.5 arch/arm/mach-exynos/dmc_init_exynos4.c

内存初始化适配，启用交错，交错大小设置为2GB（相当于不交错）

Exynos4412支持两个DDR控制器，并且支持组成双通道，1412版本的核心板只有两颗16bit DDR3（构成一颗32bit DDR3连接到片选Xm1CSn0上），因此在Exynos4412看来实际上只接了一颗DDR3。

diff --git a/arch/arm/mach-exynos/dmc_init_exynos4.c b/arch/arm/mach-exynos/dmc_init_exynos4.c
index ecddc72684..7436eeb098 100644
--- a/arch/arm/mach-exynos/dmc_init_exynos4.c
+++ b/arch/arm/mach-exynos/dmc_init_exynos4.c
@@ -26,7 +26,11 @@
 #include <config.h>
 #include <asm/arch/dmc.h>
 #include "common_setup.h"
+#if IS_ENABLED(CONFIG_TINY4412)
+#include "exynos4412_setup.h"
+#else
 #include "exynos4_setup.h"
+#endif
 
 struct mem_timings mem = {
 	.direct_cmd_msr = {
@@ -123,6 +127,9 @@ static void dmc_init(struct exynos4_dmc *dmc)
 
 	writel(mem.memconfig0, &dmc->memconfig0);
 	writel(mem.memconfig1, &dmc->memconfig1);
+#if IS_ENABLED(CONFIG_TINY4412)
+	writel((1<<31)|0x1F, &dmc->ivcontrol);
+#endif
 
 	/* Config Precharge Policy */
 	writel(mem.prechconfig, &dmc->prechconfig);

2.3.6 arch/arm/mach-exynos/exynos4412_setup.h

新增头文件：arch/arm/mach-exynos/exynos4412_setup.h

主要是定义时钟配置，DDR3时序配置。

diff --git a/arch/arm/mach-exynos/exynos4412_setup.h b/arch/arm/mach-exynos/exynos4412_setup.h
new file mode 100644
index 0000000000..dd9218c2dc
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos4412_setup.h
@@ -0,0 +1,652 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Machine Specific Values for EXYNOS4412 based board
+ *
+ * Copyright (C) 2020 FriendlyARM Electronics Co., Ltd.
+ */
+
+#ifndef _TINY4412_SETUP_H
+#define _TINY4412_SETUP_H
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200
+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+/* Bus Configuration Register Address */
+#define ASYNC_CONFIG		0x10010350
+
+/* CLK_SRC_CPU */
+#define MUX_MPLL_USER_SEL_C_FINPLL		0x0
+#define MUX_MPLL_USER_SEL_C_FOUTMPLL	0x1
+#define MUX_HPM_SEL_MOUTAPLL		0x0
+#define MUX_HPM_SEL_SCLKMPLL		0x1
+#define MUX_CORE_SEL_MOUTAPLL		0x0
+#define MUX_CORE_SEL_SCLKMPLL		0x1
+#define MUX_APLL_SEL_FILPLL		0x0
+#define MUX_APLL_SEL_MOUTMPLLFOUT	0x1
+#define CLK_SRC_CPU_VAL			((MUX_MPLL_USER_SEL_C_FOUTMPLL << 24) \
+					| (MUX_HPM_SEL_MOUTAPLL << 20) \
+					| (MUX_CORE_SEL_MOUTAPLL << 16)\
+					| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
+
+/* CLK_DIV_CPU0 */
+#define CORE2_RATIO		0x0
+#define APLL_RATIO		0x1
+#define PCLK_DBG_RATIO		0x1
+#define ATB_RATIO		0x6
+#define PERIPH_RATIO		0x0
+#define COREM1_RATIO		0x7
+#define COREM0_RATIO		0x3
+#define CORE_RATIO		0x0
+#define CLK_DIV_CPU0_VAL	((CORE2_RATIO << 28) \
+				| (APLL_RATIO << 24) \
+				| (PCLK_DBG_RATIO << 20) \
+				| (ATB_RATIO << 16) \
+				| (PERIPH_RATIO << 12) \
+				| (COREM1_RATIO << 8) \
+				| (COREM0_RATIO << 4) \
+				| (CORE_RATIO << 0))
+
+/* CLK_DIV_CPU1 */
+#define CORES_RATIO		0x5
+#define HPM_RATIO		0x0
+#define COPY_RATIO		0x6
+#define CLK_DIV_CPU1_VAL	((CORES_RATIO<<8) | (HPM_RATIO << 4) | (COPY_RATIO))
+
+/* CLK_SRC_DMC */
+#define MUX_G2D_ACP_SEL_MOUTG2D_ACP_0	0x0
+#define MUX_G2D_ACP_SEL_MOUTG2D_ACP_1	0x1
+#define MUX_G2D_ACP_1_SEL_SCLKEPLL	0x0
+#define MUX_G2D_ACP_1_SEL_SCLKVPLL	0x1
+#define MUX_G2D_ACP_0_SEL_SCLKMPLL	0x0
+#define MUX_G2D_ACP_0_SEL_SCLKAPLL	0x1
+#define MUX_PWI_SEL_XXTI		0x0
+#define MUX_PWI_SEL_XUSBXTI		0x1
+#define MUX_PWI_SEL_SCLK_HDMI24M	0x2
+#define MUX_PWI_SEL_SCLK_USBPHY0	0x3
+#define MUX_PWI_SEL_SCLK_USBPHY1	0x4
+#define MUX_PWI_SEL_SCLK_HDMIPHY	0x5
+#define MUX_PWI_SEL_SCLKMPLL		0x6
+#define MUX_PWI_SEL_SCLKEPLL		0x7
+#define MUX_PWI_SEL_SCLKVPLL		0x8
+#define MUX_MPLL_SEL_FINPLL			0x0
+#define MUX_MPLL_SEL_MOUTMPLLFOUT	0x1
+#define MUX_DPHY_SEL_SCLKMPLL		0x0
+#define MUX_DPHY_SEL_SCLKAPLL		0x1
+#define MUX_DMC_BUS_SEL_SCLKMPLL	0x0
+#define MUX_DMC_BUS_SEL_SCLKAPLL	0x1
+#define MUX_C2C_SEL_SCLKMPLL		0x0
+#define MUX_C2C_SEL_SCLKAPLL		0x1
+#define CLK_SRC_DMC_VAL			((MUX_G2D_ACP_SEL_MOUTG2D_ACP_0 << 28) \
+					| (MUX_G2D_ACP_1_SEL_SCLKEPLL << 24) \
+					| (MUX_G2D_ACP_0_SEL_SCLKMPLL << 20) \
+					| (MUX_PWI_SEL_XUSBXTI << 16) \
+					| (MUX_MPLL_SEL_MOUTMPLLFOUT << 12) \
+					| (MUX_DPHY_SEL_SCLKMPLL << 8) \
+					| (MUX_DMC_BUS_SEL_SCLKMPLL << 4) \
+					| (MUX_C2C_SEL_SCLKMPLL << 0))
+
+/* CLK_DIV_DMC0 */
+#define DMCP_RATIO		0x1
+#define DMCD_RATIO		0x1
+#define DMC_RATIO		0x1
+#define DPHY_RATIO		0x1
+#define ACP_PCLK_RATIO		0x1
+#define ACP_RATIO		0x3
+#define CLK_DIV_DMC0_VAL	((DMCP_RATIO << 20) \
+				| (DMCD_RATIO << 16) \
+				| (DMC_RATIO << 12) \
+				| (DPHY_RATIO << 8) \
+				| (ACP_PCLK_RATIO << 4)	\
+				| (ACP_RATIO << 0))
+
+/* CLK_DIV_DMC1 */
+#define DPM_RATIO		0x1
+#define DVSEM_RATIO		0x1
+#define C2C_ACLK_RATIO	0x1
+#define PWI_RATIO		0x7
+#define C2C_RATIO		0x1
+#define G2D_ACP_RATIO	0x3
+#define CLK_DIV_DMC1_VAL	((DPM_RATIO << 24) \
+				| (DVSEM_RATIO << 16) \
+				| (C2C_ACLK_RATIO << 12) \
+				| (PWI_RATIO << 8) \
+				| (C2C_RATIO << 4) \
+				| (G2D_ACP_RATIO << 0))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_SEL_ACLK_133	0x0
+#define MUX_ONENAND_SEL_ACLK_160	0x1
+#define MUX_ACLK_133_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_133_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_160_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_160_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_100_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_100_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_200_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_200_SEL_SCLKAPLL	0x1
+#define MUX_VPLL_SEL_FINPLL		0x0
+#define MUX_VPLL_SEL_FOUTVPLL		0x1
+#define MUX_EPLL_SEL_FINPLL		0x0
+#define MUX_EPLL_SEL_FOUTEPLL		0x1
+#define MUX_ONENAND_1_SEL_MOUTONENAND	0x0
+#define MUX_ONENAND_1_SEL_SCLKVPLL	0x1
+#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL_ACLK_133 << 28) \
+					| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
+					| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
+					| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
+					| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
+					| (MUX_VPLL_SEL_FOUTVPLL << 8) \
+					| (MUX_EPLL_SEL_FOUTEPLL << 4)\
+					| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
+
+/* CLK_SRC_TOP1 */
+#define MUX_ACLK_400_MCUISP_SUB_SEL_FINPLL	0x0
+#define MUX_ACLK_400_MCUISP_SUB_SEL_DIVOUT_ACLK_400_MCUISP	0x1
+#define MUX_ACLK_200_SUB_SEL_FINPLL	0x0
+#define MUX_ACLK_200_SUB_SEL_DIVOUT_ACLK_200	0x1
+#define MUX_ACLK_266_GPS_SUB_SEL_FINPLL	0x0
+#define MUX_ACLK_266_GPS_SUB_SEL_DIVOUT_ACLK_266_GPS	0x1
+#define MUX_MPLL_USER_SEL_T_FINPLL	0x0
+#define MUX_MPLL_USER_SEL_T_SCLKMPLL	0x1
+#define MUX_ACLK_400_MCUISP_SEL_SCLKMPLL_USER_T	0x0
+#define MUX_ACLK_400_MCUISP_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_266_GPS_SEL_SCLKMPLL_USER_T	0x0
+#define MUX_ACLK_266_GPS_SEL_SCLKAPLL	0x0
+#define CLK_SRC_TOP1_VAL	((MUX_ACLK_400_MCUISP_SUB_SEL_DIVOUT_ACLK_400_MCUISP << 24) \
+					| (MUX_ACLK_200_SUB_SEL_DIVOUT_ACLK_200 << 20) \
+					| (MUX_ACLK_266_GPS_SUB_SEL_DIVOUT_ACLK_266_GPS << 16) \
+					| (MUX_MPLL_USER_SEL_T_SCLKMPLL << 12) \
+					| (MUX_ACLK_400_MCUISP_SEL_SCLKMPLL_USER_T << 8) \
+					| (MUX_ACLK_266_GPS_SEL_SCLKMPLL_USER_T << 4))
+
+/* CLK_DIV_TOP */
+#define ACLK_400_MCUISP_RATIO	0x0
+#define ACLK_266_GPS_RATIO	0x0
+#define ONENAND_RATIO		0x1
+#define ACLK_133_RATIO		0x5
+#define ACLK_160_RATIO		0x4
+#define ACLK_100_RATIO		0x7
+#define ACLK_200_RATIO		0x0
+#define CLK_DIV_TOP_VAL		((ACLK_400_MCUISP_RATIO << 24)	\
+				| (ACLK_266_GPS_RATIO << 20)	\
+				| (ONENAND_RATIO << 16)	\
+				| (ACLK_133_RATIO << 12)\
+				| (ACLK_160_RATIO << 8)	\
+				| (ACLK_100_RATIO << 4)	\
+				| (ACLK_200_RATIO << 0))
+
+/* CLK_SRC_LEFTBUS */
+#define MUX_MPLL_USER_SEL_L_FINPLL	0x0
+#define MUX_MPLL_USER_SEL_L_FOUTMPLL	0x1
+#define MUX_GDL_SEL_SCLKMPLL	0x0
+#define MUX_GDL_SEL_SCLKAPLL	0x1
+#define CLK_SRC_LEFTBUS_VAL	((MUX_MPLL_USER_SEL_L_FOUTMPLL << 4) \
+				| (MUX_GDL_SEL_SCLKMPLL << 0))
+
+/* CLK_DIV_LEFTBUS */
+#define GPL_RATIO		0x1
+#define GDL_RATIO		0x3
+#define CLK_DIV_LEFTBUS_VAL	((GPL_RATIO << 4) | (GDL_RATIO))
+
+/* CLK_SRC_RIGHTBUS */
+#define MUX_MPLL_USER_SEL_R_FINPLL	0x0
+#define MUX_MPLL_USER_SEL_R_FOUTMPLL	0x1
+#define MUX_GDR_SEL_SCLKMPLL	0x0
+#define MUX_GDR_SEL_SCLKAPLL	0x1
+#define CLK_SRC_RIGHTBUS_VAL	((MUX_MPLL_USER_SEL_R_FOUTMPLL << 4) \
+				| (MUX_GDR_SEL_SCLKMPLL << 0))
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO		0x1
+#define GDR_RATIO		0x3
+#define CLK_DIV_RIGHTBUS_VAL	((GPR_RATIO << 4) | (GDR_RATIO))
+
+/* CLK_SRS_FSYS: 6 = SCLKMPLL */
+#define SATA_SEL_SCLKMPLL	0
+#define SATA_SEL_SCLKAPLL	1
+
+#define MMC_SEL_XXTI		0
+#define MMC_SEL_XUSBXTI		1
+#define MMC_SEL_SCLK_HDMI24M	2
+#define MMC_SEL_SCLK_USBPHY0	3
+#define MMC_SEL_SCLK_USBPHY1	4
+#define MMC_SEL_SCLK_HDMIPHY	5
+#define MMC_SEL_SCLKMPLL	6
+#define MMC_SEL_SCLKEPLL	7
+#define MMC_SEL_SCLKVPLL	8
+
+#define MMCC0_SEL		MMC_SEL_SCLKMPLL
+#define MMCC1_SEL		MMC_SEL_SCLKMPLL
+#define MMCC2_SEL		MMC_SEL_SCLKMPLL
+#define MMCC3_SEL		MMC_SEL_SCLKMPLL
+#define MMCC4_SEL		MMC_SEL_SCLKMPLL
+#define CLK_SRC_FSYS_VAL	((SATA_SEL_SCLKMPLL << 24) \
+				| (MMCC4_SEL << 16) \
+				| (MMCC3_SEL << 12) \
+				| (MMCC2_SEL << 8) \
+				| (MMCC1_SEL << 4) \
+				| (MMCC0_SEL << 0))
+
+/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
+/* CLK_DIV_FSYS1 */
+#define MMC0_RATIO		0xF
+#define MMC0_PRE_RATIO		0x0
+#define MMC1_RATIO		0xF
+#define MMC1_PRE_RATIO		0x0
+#define CLK_DIV_FSYS1_VAL	((MMC1_PRE_RATIO << 24) \
+				| (MMC1_RATIO << 16) \
+				| (MMC0_PRE_RATIO << 8) \
+				| (MMC0_RATIO << 0))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO		0x7
+#define MMC2_PRE_RATIO		0x0
+#define MMC3_RATIO		0x7
+#define MMC3_PRE_RATIO		0x4
+#define CLK_DIV_FSYS2_VAL	((MMC3_PRE_RATIO << 24) \
+				| (MMC3_RATIO << 16) \
+				| (MMC2_PRE_RATIO << 8) \
+				| (MMC2_RATIO << 0))
+
+/* CLK_DIV_FSYS3 */
+#define MMC4_RATIO		0xF
+#define MMC4_PRE_RATIO		0x0
+#define CLK_DIV_FSYS3_VAL	((MMC4_PRE_RATIO << 8) \
+				| (MMC4_RATIO << 0))
+
+/* CLK_SRC_PERIL0 */
+#define UART_SEL_XXTI		0
+#define UART_SEL_XUSBXTI	1
+#define UART_SEL_SCLK_HDMI24M	2
+#define UART_SEL_SCLK_USBPHY0	3
+#define UART_SEL_SCLK_USBPHY1	4
+#define UART_SEL_SCLK_HDMIPHY	5
+#define UART_SEL_SCLKMPLL	6
+#define UART_SEL_SCLKEPLL	7
+#define UART_SEL_SCLKVPLL	8
+
+#define UART0_SEL		UART_SEL_SCLKMPLL
+#define UART1_SEL		UART_SEL_SCLKMPLL
+#define UART2_SEL		UART_SEL_SCLKMPLL
+#define UART3_SEL		UART_SEL_SCLKMPLL
+#define UART4_SEL		UART_SEL_SCLKMPLL
+#define CLK_SRC_PERIL0_VAL	((UART4_SEL << 16) \
+				| (UART3_SEL << 12) \
+				| (UART2_SEL << 8) \
+				| (UART1_SEL << 4) \
+				| (UART0_SEL << 0))
+
+/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
+/* CLK_DIV_PERIL0 */
+#define UART0_RATIO		7
+#define UART1_RATIO		7
+#define UART2_RATIO		7
+#define UART3_RATIO		7
+#define UART4_RATIO		7
+#define CLK_DIV_PERIL0_VAL	((UART4_RATIO << 16) \
+				| (UART3_RATIO << 12) \
+				| (UART2_RATIO << 8) \
+				| (UART1_RATIO << 4) \
+				| (UART0_RATIO << 0))
+
+/* Clock Source CAM/FIMC */
+/* CLK_SRC_CAM */
+#defi