Preface——Cortex-A Series Programmer's Guide

1. The ARM Architecture Reference Manual (known as ARM ARM) 是任何ARM的程序设计人员都必须要读的一本手册。对ARMv7指令集、编程的模式、寄存器、调试特点和存储模式有全面的的介绍。这本手册我已有。

2. 当这本书与ARM ARM出现不一致时,遵从ARM ARM上所描述的。

3. 还有另外一本手册Technical Reference Manual是关于处理器的详细说明,关于Cortex A8的手册手机和电脑都有

  有个网站:http://infocenter.arm.com/help/index.jsp,已保存在360浏览器的收藏夹里

4. 术语的简写:

AAPCSARM 		Architecture Procedure Call Standard.
ABI   			Application Binary Interface.
ACP   			Accelerator Coherency Port.
AHB   			Advanced High-Performance Bus.
AMBA 			Advanced Microcontroller Bus Architecture.
AMP   			Asymmetric Multi-Processing.
APB   			Advanced Peripheral Bus.
ARM ARM   		The ARM Architecture Reference Manual.
ASIC   			Application Specific Integrated Circuit.
APSR   			Application Program Status Register.
ASID   			Address Space ID.
ATPCS   		ARM Thumb Procedure Call Standard.
AXI   			Advanced eXtensible Interface.
BE8   			Byte Invariant Big-Endian Mode.
BSP   			Board Support Package.
BTAC 			Branch Target Address Cache.
BTB   			Branch Target Buffer.
CISC 			Complex Instruction Set Computer.
CP15 			Coprocessor 15 - Systemcontrol coprocessor.
CPSR 			Current Program Status Register.
DAP   			Debug Access Port.
DBX   			Direct Bytecode Execution.
DDR   			Double Data Rate (SDRAM).
DMA   			Direct Memory Access.
DMB   			Data Memory Barrier.
DS-5 			The ARM Development Studio.
DSB   			Data Synchronization Barrier.
DSP  			Digital Signal Processing.
DSTREAM 		An ARM debug and trace unit.
DVFS 			Dynamic Voltage/Frequency Scaling.
EABI 			Embedded ABI.
ECC 			Error Correcting Code.
ECT 			Embedded Cross Trigger.
ETB 			Embedded Trace Buffer
ETM   			Embedded Trace Macrocell
FIQ   			An interrupt type (formerly fast interrupt).
FPSCR 			Floating-Point Status and Control Register.
GCC   			GNU Compiler Collection.
GIC   			Generic Interrupt Controller.
GIF   			Graphics Interchange Format.
GPIO   			General Purpose Input/Output.
Gprof   		GNU profiler.

Harvard architecture Architecture with physically separate storage and signal pathways for instructions and data.

IDE 			Integrated development environment.
IPA 			Intermediate Physical Address.
IRQ 			Interrupt Request (normally external interrupts).
ISA 			Instruction Set Architecture.
ISB 			Instruction Synchronization Barrier.
ISR 			Interrupt Service Routine.
Jazelle 		The ARM bytecode acceleration technology.
JIT   			Just In Time.
L1/L2 			Level 1/Level 2.
LPAE   			Large Physical Address Extension.
LSB  			Least Significant Bit.
MESI   			A cache coherency protocol with four states, Modified, Exclusive, Shared and Invalid.
MMU   			Memory Management Unit.
MPU   			Memory Protection Unit.
MSB   			Most Significant Bit.
NEON 			The ARM Advanced SIMD Extensions.
NMI   			Non-Maskable Interrupt.
Oprofile   		A Linux system profiler.
QEMU   			A processor emulator.
PCI   			Peripheral Component Interconnect. A computer bus standard.
PIPT 			Physically Indexed, Physically Tagged.
PLE  	 		Preload Engine.
PMU   			Performance Monitor Unit.
PoC   			Point of Coherency.
PoU   			Point of Unification.
PPI   			Private Peripheral Input.
PSR   			Program Status Register.
PTE   			Page Table Entry.
RCT   			Runtime Compiler Target.
RISC   			Reduced Instruction Set Computer.
RVCT   			RealView Compilation Tools (the “ARM Compiler”).
SCU   			Snoop Control Unit.
SGI   			Software Generated Interrupt.
SIMD 			Single Instruction, Multiple Data.
SiP   			System in Package.
SMP   			Symmetric Multi-Processing.
SoC   			System on Chip.
SP   			Stack Pointer.
SPI   			Shared Peripheral Interrupt.
SPSR   			Saved Program Status Register.
Streamline   		A graphical performance analysis tool.
SVC   			Supervisor Call. (Previously SWI.)
SWI   			Software Interrupt.
SYS   			System Mode.
TAP   			Test Access Port (JTAG Interface).
TCM   			Tightly Coupled Memory.
TDMI 			Thumb, Debug, Multiplier, ICE.
TEX   			Type Extension.
Thumb 			An instruction set extension to ARM.
Thumb-2  	 	A technology extending the Thumb instruction set to support both 16- and 32-bit instructions.
TLB   			Translation Lookaside Buffer.
TLS   			Thread Local Storage.
TrustZone 		The ARM security extension.
TTB   			Translation Table Base.
UAL   			Unified Assembly Language.
UART 			Universal Asynchronous Receiver/Transmitter.
UEFI 			Unified Extensible Firmware Interface.
U-Boot   		A Linux Bootloader.
USR   			User mode, a non-privileged processor mode.
VFP   			The ARM floating-point instruction set. Before ARMv7, the VFP extension was called the Vector Floating-Point architecture, and was used for vector operations.
VIC   			Vectored Interrupt Controller.
VIPT   			Virtually Indexed, Physically Tagged.
VMID   			Virtual Machine ID.
VMSA   			Virtual Memory Systems Architecture.
XN   			Execute Never.

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This Cortex-A Series Programmer’s Guide is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this Cortex-A Series Programmer’s Guide may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this Cortex-A Series Programmer’s Guide. Your access to the information in this Cortex-A Series Programmer’s Guide is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations of the information herein infringe any third party patents. This Cortex-A Series Programmer’s Guide is provided “as is”. ARM makes no representations or warranties, either express or implied, included but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, that the content of this Cortex-A Series Programmer’s Guide is suitable for any particular purpose or that any practice or implementation of the contents of the Cortex-A Series Programmer’s Guide will not infringe any third party patents, copyrights, trade secrets, or other rights. This Cortex-A Series Programmer’s Guide may include technical inaccuracies or typographical errors. To the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation any direct loss, lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages, however caused and regardless of the theory of liability, arising out of or related to any furnishing, practicing, modifying or any use of this Programmer’s Guide, even if ARM has been advised of the possibility of such damages. The information provided herein is subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries. You agree to comply fully with all laws and regulations of the United States and other countries (“Export Laws”) to assure that neither the information herein, nor any direct products thereof are; (i) exported, directly or indirectly, in violation of Export Laws, either to any countries that are subject to U.S. export restrictions or to any end user who has been prohibited from participating in the U.S. export transactions by any federal agency of the U.S. government; or (ii) intended to be used for any purpose prohibited by Export Laws, including, without limitation, nuclear, chemical, or biological weapons proliferation. Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Copyright © 2011, 2012 ARM Limited, 110 Fulbourn Road Cambridge, CB1 9NJ, England This document is Non-Confidential but any disclosure by you is subject to you providing notice to and the

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