usb high speed chirp

介绍

所有 USB2.0 连接都以低速 (LS) 或全速 (FS) 模式开始。如果设备或集线器上游端口能够进行高速 (HS) 操作，则设备或集线器将首先通过在准备连接时将 D+ 线拉高来发出 FS 操作信号。

一旦 USB 主机或集线器下游端口检测到连接的设备，USB 复位线状态由主机/集线器下游端口驱动，并开始一个称为“高速chirp”的过程。

如果设备/集线器上行端口和主机/集线器下行端口都支持 HS 操作并且 HS Chirp 成功，则链路转换到 HS 操作模式。

chirp 握手是高速特有信号，高速协商是在reset的(10ms时间)过程中进行的。

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Answer

High-Speed Chirp Sequence

 

Line-state details

HS Chirp Sequence in written form:A--->1,B-->2,...,I-->9

Step	Host or Hub DFP Action	Device or Hub UFP Action	D+ Voltage	D- Voltage	Duration
1	USB interface is enabled. Full-Speed Host Terminations Enabled: 15k pull-down resistors applied to D+ and D- Host enables VBUS to supply 5V to the port.		Low (<100mV)	Low (<100mV)	undefined
2		1.5k Pull-Up resistor applied to D+	2.7V – 3.3V	Low (<100mV)	undefined
3	Bus Reset is driven. HS terminations applied: 50Ohm resistors to GND on D+ and D-		Low (<100mV)	Low (<100mV)	2.5µs (min) 6ms (max)
4		17.78mA current driver enabled on D- line (Chirp-K line state)	Low (<100mV)	~800mV	1ms (min) ~7ms (max)
5		17.78mA current driver disabled	Low (<100mV)	Low (<100mV)	40µs (min) 60µs (max)
6	17.78mA current drive enabled on D- only (Chirp-K), then on D+ only (Chirp-J), alternating continuously		Low (<100mV)	~800mV	40-60µs
			~800mV	Low (<100mV)	40-60µs
			Low (<100mV)	~800mV	40-60µs
			~800mV	Low (<100mV)	40-60µs
			~800mV	Low (<100mV)	40-60µs
			~800mV	Low (<100mV)	40-60µs
7	17.78mA current drive enabled on D- only (Chirp-K), then on D+ only (Chirp-J), alternating continuously	After 3 complete K-J line state pairs are detected (as driven by host or Hub DFP): - 1.5k Pull-up resistor on D+ disabled. - HS 45Ohm terminations applied to D+ and D-	Low (<100mV)	~400mV	40-60µs
			~400mV	Low (<100mV)	40-60µs
			REPEAT V V V V V V	REPEAT V V V V V V	REPEAT V V V V V V
8	Alternative Chirp-K/Chirp-J signals stop		Low (<100mV)	Low (<100mV)	< 10ms from start of step 3
9	HS communication with attached device/Hub may begin.		When bus is inactive: D+/D- = <100mV When bus is active: ~400mV differential signals		> 10ms from start of step 3