Intel® 64 and IA-32 Architectures：0002-NOTATIONAL CONVENTIONS(符号约定)

This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. This notation is described below.

这本手册使用特定的符号来表示数据结构（格式）、用符号代表的指令以及十六进制和二进制数字，这些特定的符号描述如下。

2.1 Bit and Byte Order(Bit 和 Byte次序)

In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. Intel 64 and IA-32 processors are “little endian” machines; this means the bytes of a word are numbered starting from the least significant byte. See Figure 1-1.

下图展示的是内存中的数据结构，较小的地址出现在图的底部，地址向上增长。Bit位从右向左被编号。当某一位的值等于2时向高位进位。Intel 64 and IA-32 处理器是小尾机，这意味着，一个字的两个字节（在内存中）是从地址较小的那个字节开始的。见图1-1。

Figure 1-1. Bit and Byte Order

2.2 Reserved Bits and Software Compatibility(保留位和软件兼容性)

In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked asreserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable.

在许多寄存器和内存布局描述中，某些特定的位被标记为“保留的”。当某些位被标记为“保留的”时，实际上是为了将来的处理器的兼容性，软件应该认为这些位是在未来有却未知的效果。保留位的行为不仅应该视为未定义，并且是不可预知的。

Software should follow these guidelines in dealing with reserved bits:

•       Do not depend on the states of any reserved bits when testing the values of registers that contain such bits. Mask out the reserved bits before testing.

•       Do not depend on the states of any reserved bits when storing to memory or to a register.

•       Do not depend on the ability to retain information written into any reserved bits.

•       When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register.

软件应该遵从下面的原则来处理这些“保留的”位：

•       一定不要依赖于任何保留位的状态，当测试一个包含保留位的寄存器的值时，在测试之前应该将保留位屏蔽。

•       一定不要依赖于任何保留位的状态，当数据被保存到寄存器或是内存中时。

•       一定不要依赖于任何保留位保存数据信息的能力。

•       当加载一个寄存器时要根据文档的指示加载保留的位，(即使如此) ，或者使用之前从这个寄存器中读取的值重新加载。

Note

Avoid any software dependence upon the state of reserved bits in Intel 64 and IA-32 registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors.

注意

在Intel 64 和IA-32 寄存器中，避免任何软件依赖于保留位的状态。依赖于寄存器保留位的值将使得软件依赖于处理器不明确的行为。依赖于这些保留位的值的程序会产生与未来处理器不兼容的风险。

2.2.1 Instruction Operands(指令操作数)

When instructions are represented symbolically, a subset of the IA-32 assembly language is used. In this subset, an instruction has the following format:

label: mnemonic argument1, argument2, argument3

where:

•        A label is an identifier which is followed by a colon.

•        A mnemonic is a reserved name for a class of instruction opcodes which have the same function.

•        The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands, depending on the opcode. When present, they take the form of either literals or identifiers for data items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items declared in another part of the program (which may not be shown in the example).

当指令被符号化时，IA-32汇编语言的一个子集便被使用了。在这个子集中，一条指令有如下的格式：

标号:助词符 参数1,参数2,参数3

在这里：

•        标号，是一个标识符，标号后面通常跟着冒号

•        助记符，是汇编语言中的保留字，可以代替指令操作码，和指令有同样的功能

•        操作数，即参数1、参数2、参数3是可选的，可以没有操作数，最多可以有三个操作数，这取决于操作码。操作数通常以文字或数据项的标识符形式出现。操作数标识符不是寄存器的保留字就是在程序的其它地方声明的数据项（这点在上面的例子中没有体现）。

When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left operand is the destination.

For example:

LOADREG: MOV EAX, SUBTOTAL

In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand, and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.

当两个操作数出现在一个算法或是逻辑指令中时，右边的操作数是源操作数，左边的操作数是目的操作数。比如：

LOADREG: MOV EAX, SUBTOTAL

在这个例子中，LOADREG是一个标号，MOV是操作码的助记符，EAX是目的操作数，SUBTOTAL是源操作数。在许多汇编语言中，源操作数和目的操作数是相反的顺序。

2.3 Hexadecimal and Binary Numbers(16进制和2进制数)

Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for example, 0F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.

Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might arise.

十六进制数是以一个由H结尾的字符串来表示的（比如：0F82EH），一个十六进制数是由以下字符组成的集合：0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F。

二进制数是由许多0和1组成的字符串，有时会以B结尾（比如：1010B）。字符“B”会在产生歧义时出现。

2.4 Segmented Addressing(段寻址)

The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes. Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes memory. The range of memory that can be addressed is called an address space.

处理器使用字节地址。这意味着内存的组织形式和访问形式都是以一系列的字节为基础。不管是一个字节还是多个字节被访问，一个字节的地址就可以定位一个或多个节的地址。内存中可以被寻址的范围被称为一个地址空间。

The processor also supports segmented addressing. This is a form of addressing where a program may have many independent address spaces, called segments. For example, a program can keep its code (instructions) and stack in separate segments. Code addresses would always refer to the code space, and stack addresses would always refer to the stack space. The following notation is used to specify a byte address within a segment:

       Segment-register:Byte-address

For example, the following segment address identifies the byte at address FF79H in

the segment pointed by the DS register:

       DS:FF79H

The following segment address identifies an instruction address in the code segment.

The CS register points to the code segment and the EIP register contains the address

of the instruction.

       CS:EIP

处理器同样支持段寻址。这也是寻址的一种方式，一个程序可以有许多独立的地址空间，称为段。比如，一个程序可以将它的代码（指令集合）和栈保持在相对独立的段中。代码寻址时只是涉及到代码段的地址空间，栈寻址只是涉及到栈段的地址空间。下面的符号表示的是在一个段内的某个字节地址：

Segment-register:Byte-address

比如，下面的段地址标识了使用DS寄存器指出的段中的的一个字节地址FF79H：

DS:FF79H

再如，下面的段地址标识了一个在代码段中的一个指令地址。CS寄存器指出了代码段的地址，EIP寄存器则包含了指令的地址。

CS:EIP

2.5 A New Syntax for CPUID, CR, and MSR Values(CPUID,CR和MSR的新语法)

Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information. See Figure 1-2.

可以通过 CPUID 指令、检查控制寄存器的某些位、读特定模式的寄存器来得到功能标记、状态和系统信息。我们正在形成一种新语法来表现这些信息。见图1-2。

 

Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation

2.6 Exceptions(异常)

An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the error. An example of the notation used to show an exception and error code is shown below:

       #PF(fault code)

This example refers to a page-fault exception under conditions where an error code naming a type of fault is reported. Under some conditions, exceptions that produce error codes may not be able to report an accurate code. In this case, the error code is zero, as shown below for a general-protection exception:

       #GP(0)

一个异常是一个事件，典型地，当一条指令发生错误时就会产生异常。比如，试图被0除时会抛出异常。当然，许多异常，比如断点，发生在某些其它的条件下。许多异常会提供错误代码。一个错误代码报告了关于这个异常的额外的信息。下面是一个展示异常及其错误代码的例子：

#PF(fault code)

这个例子指出了一个页错误异常，这个异常的错误代码为fault code。在许多条件下，一个错误代码并不是准确的错误代码。在这种情况下，错误代码是0，比如下面的通用保护异常：

#GP(0)