LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY moore IS
PORT
(clk ,reset:IN std_logic;
state_inputs:IN std_logic_vector(0 TO 1);
comb_outputs:OUT std_logic_vector(0 TO 1)
);
END moore;
ARCHITECTURE be OF moore IS
TYPE fsm_st IS (S0,S1,S2,S3,S4);--状态的枚举类型定义
SIGNAL current_state,next_state:fsm_st ;--状态信号的定义
BEGIN
Reg:PROCESS(reset,clk ) --时序进程
BEGIN
IF reset='1' THEN current_state<=S0; --异步复位
ELSIF rising_edge(clk )THEN
current_state<=next_state; --状态转换
END IF;
END PROCESS reg;
corn:PROCESS(current_state,state_Inputs) --组合进程
BEGIN
CASE current_state IS
W
USE IEEE.std_logic_1164.ALL;
ENTITY moore IS
PORT
(clk ,reset:IN std_logic;
state_inputs:IN std_logic_vector(0 TO 1);
comb_outputs:OUT std_logic_vector(0 TO 1)
);
END moore;
ARCHITECTURE be OF moore IS
TYPE fsm_st IS (S0,S1,S2,S3,S4);--状态的枚举类型定义
SIGNAL current_state,next_state:fsm_st ;--状态信号的定义
BEGIN
Reg:PROCESS(reset,clk ) --时序进程
BEGIN
IF reset='1' THEN current_state<=S0; --异步复位
ELSIF rising_edge(clk )THEN
current_state<=next_state; --状态转换
END IF;
END PROCESS reg;
corn:PROCESS(current_state,state_Inputs) --组合进程
BEGIN
CASE current_state IS
W