基于Verilog HDL的流水灯

module FLOAT_LIGHT(CLOCK_50,SW,LEDR);//全局复位信号SW[17]
input [17:0]SW;
output[17:0]LEDR;
input CLOCK_50;//50M赫兹的时钟
reg clk_1hz;
reg clk_10hz;
reg clk_20hz;
reg clk_60hz;
reg clk;
reg state;
reg [26:0]cnt1hz;
reg [26:0]cnt10hz;
reg [26:0]cnt20hz;
reg [26:0]cnt60hz;
reg [17:0]cnt2;
//50M赫兹的时钟分频为1赫兹
always@(posedge CLOCK_50 or negedge SW[17])
if (!SW[17])
begin cnt1hz<=0;clk_1hz<=0;end
else if(cnt1hz==27'd50_000_000)
begin cnt1hz<=27'b0;clk_1hz<=1;end
else
begin cnt1hz<=cnt1hz+1;clk_1hz<=0;end
//50M赫兹的时钟分频为10赫兹
always@(posedge CLOCK_50 or negedge SW[17])
if (!SW[17])
begin cnt10hz<=0;clk_10hz<=0;end
else if(cnt10hz==27'd50_000_00)
begin cnt10hz<=27'b0;clk_10hz<=1;end
else
begin cnt10hz<=cnt10hz+1;clk_10hz<=0;end
//50兆赫兹的时钟分频为20赫兹
always@(posedge CLOCK_50 or negedge SW[17])
if (!SW[17])
begin cnt20hz<=0;clk_20hz<=