31 UART

本章描述在S3C6410X精简指令集的微处理器中的通用异步收发器（UART）串口。

31.1 综述

S3C6410X通用异步收发器提供了四个独立的异步串口I/O端口，每个异步I/O串口能使用基本的中断或者DMA模式.换句话说，普通异步收发器能够支持最大每秒3Mbps，每一个通用异步收发器包含了两个64字节的FIFO，用于接收和发送。

S3C6410X通用异步收发器包含了可编程的波特率，红外收发器，一个或两个停止位的插入，5-8位的数据宽度和奇偶校验。

每一个通用异步收发器包含一个波特率的生产器，发送器，接收器和一个控制单元，如图31-1，波特率的生产器被PCLK，EXT_UCLK0 or EXT_UCLK1提供，发送器和接收器包含64字节的先进先出区域和数据的缓存。在被发送之前，数据写到先进先出单元，然后拷贝到发送的缓存区。然后数据被发送数据引脚（TxDn）移出。同时，被接收器引脚（RxDn）接收到的数据被缓存，然后拷贝到FIFO。

31.2 特性

通用异步收发器的特性包括：

带有DMA或者中断操作的RxD0, TxD0, RxD1, TxD1, RxD2, TxD2, RxD3 and TxD3

带有红外1.0的通用异步收发器的0, 1, 2 和 3 XX，和64字节的FIFO(不知道怎么翻译了，知道的回复一下)

UART Ch 0 and 1 with nRTS0, nCTS0, nRTS1, and nCTS1

通用异步收发器支持高速传输

31.3 描述

接下来的章节将会描述通用异步收发器的操作，包括发送数据，接收数据，产生中断， 产生波特率， Loopback mode(回调模式),红外模式和自动流控制。

31.3.1 发送数据

发送的数据帧是可以编程的，它包含1个开始位，5-8个数据位， 一个可选的奇偶校验位和1到两个停止位， 它被行控制寄存器(ULCONn)定义，发送器也能够产生中断控制，它能强迫串口在一针的发送时间输出逻辑0。这个中断信号块在一个传输命令完成之后传输中断信号，在中断信号传输之后，它能够继续的发送数据到Tx FIFO(当Tx保持在非空的状态下)

31.3.2 数据的接收

像发送一样，接收的数据帧也是可标称的，它包含一个开始位，5到8个数据位和一个可选的奇偶校验位和在行控制结存器中的(ULCONn)的1到2个结束位，接收器能检测溢出错误，奇偶错误，帧错误和中断环境，并且每一个错误都会设置错误标志位。

溢出错误指明在旧数据在读之前，被新数据覆写了；

奇偶错误表明接收器已经检测到了一个未知的奇偶情况

帧错误指定接收的数据没有一个停止位的校验

中断环境指明在超过一个帧的时间以上RxDn的输入是逻辑0

当超过3条指令时间(这个时间跟指令字长的环境有关)没有接收到任何数据并且在FIFO模式下Rx FIFO 不为空。

This chapter describes the universal asynchronous receiver/transmitter (UART) serial ports included in the S3C6410X RISC microprocessor.

31.1 OVERVIEW

The S3C6410X UART provide four independent asynchronous serial I/O (SIO) ports.Each of asynchronous serial  I/O (SIO) ports can operate in interrupt-based or DMA-based mode. In other words, the UART can generate an interrupt or a DMA request to transfer data between MEM and the UART. the UART can support bit rates of maximum 3Mbps. each UART channel contains two 64-byte FIFO's for both reception and transmission.

The s3c6410X UART includes programmable baud rates, infra-red(IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.

Each UART contains a baud-rate gennerator , a transmitter, a receiver and a control unit, as shown in Figure 31-1. The baud-rate generator can be clocked by PCLK,EXT_UCLK0 or EXT_UCLK1. The transmitter and the receiver contain 64-byte FIFOs and data shifters. Data is written to FIFO and then copied to the transmit shifter befor being transmitted. The data is then shifted out by the transmit data pin (TxDn). meanwhile,received data is shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter.

31.2 FEATURES

RxD0, TxD0, RxD1, TxD1, RxD2, Txd2, Rxd3 and TxD3 with DMA-based or interrupt-based operation

UART Ch 0, 1, 2 and 3 with lrD 1.0 & 64

UART Ch 0 and 1 with nRTS0, nCTS0, nRTS1, and nCTS1

Supports high-speed operation in UART

Supports handshake transmit/receive

31.3 DESCRIPTION

The following sections describe the UART operations that include data trasmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infra-red mode, and auto flow control.

31.3.1 DATA TRANSMISSION

The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register(ULCONn).The transmitter can also produce the break control, which force the serial output to logic 0 state for one frame transmission time. This block trasmits break signals after the present transmission word is transmitted completely. After the break signal transmission, it continuously transmits data into the Tx FIFO (Tx holding register in the case of Non-FIFO mode).

31.3.2 DATA RECEPTION

Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (ULCONn). The receiver can detect overrun error, parity error, frame error and break condition, each of which can set an error flag.

The overrun error indicates that new data has overwritten the old data before the old data has been read.

The parity error indicates that the receiver has detected an unexpected parity condition.

The frame error indicates that the received dadta does not have a valid stop bit.

The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one frame transmission time.

Receive time-out condition occurs when it does not receive any data during the 3 word time (this interval follows the setting of Word Length bit) and the Rx FIFO is not empty in the FIFO mode.