STM32 VDDA和VDD

采用STM32F103RCT6 ，按照技术手册 Vref内部已与Vdda相连，而Vdda是为ADC，复位电路，RC PLL供电的。
要求：6组PCBA的ADC,DAC尽量相同

问题：VDDA和VDD的电压每个PCBA相差大，导致ADC,DAC相差大

查询：

• VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 12: Power supply scheme

5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External main supply voltage (including VDDA and VDD) (1)

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. –0.3 4.0 V VIN(2)

2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum allowed injected current values. Input voltage on five volt tolerant pin VSS − 0.3 VDD + 4.0 Input voltage on any other pin VSS −0.3 4.0 |ΔVDDx| Variations between different VDD power pins - 50 mV |VSSX −VSS| Variations between all the different ground pins(3) 3. Include VREF- pin.

2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation.

解决方法：由于对DAC、AD要求高，VDDA采用独立Vref一个基准源的，VDD采用LDO，考虑上电时序，采用LDO给基准源供电，并且VDD与VDDA相差<300mV