usb host controller

1. 主机控制器(Host Controller)

      • UHCI: Universal Host Controller Interface (通用主机控制接口, USB1.0/1.1)
      • OHCI: Open Host Controller Interface (开放主机控制接口,USB1.0/1.1)
      • EHCI: Enhanced Host Controller Interface (用于USB2.0高速设备的“增强主机控制接口”)    

     USB的拓扑结构决定了主机控制器就是最高统帅,没有主机控制器的要求设备永远不能主动发数据。所以主机控制器在USB的世界里扮演着重要的角色,它是幕后操纵者。

     比如说Host发送Setup包获取设备描述符是怎么发出去的?

    这个过程包含很多信息,比如:如何在D+和D-这两根线上传过去的、又传过来的。  这一切的工作都是主机控制器给我们做的。USB Host控制器的规范有很多种这里只介绍混得不错的EHCI和OHCI。这个EHCI主要针对高速的USB设备。如果要操作全速和低速可以考虑OHCI。

 

      • 什么是USB controller?

   USB 设备和主机的接口就是host controller,一个主机可以支持多个host controller比如分别属于不同厂商的。那么USB host controller 本身是做什么的? controller(控制器):用于控制。控制什么?控制所有的USB设备的通信。

      CPU把要做的事情分配给主机控制器,然后自己想干什么就干什么去,主机控制器替他去完成剩下的事情,事情办完了再通知CPU。否则让CPU去盯着每一个设备做每一件事情,那是不现实的。

      控制器的主要工作是什么? 把数扔出去,把数拿回来。绝对不应该偷偷加工数据。

      主机控制器控制总线上包的传输, 使用1ms或125us的帧。在每帧的开始时,主机控制器产生一个帧开始包(SOF: Start of Frame)。
      SOF包用于同步帧的开始和跟踪帧的数目。包在帧中被传输,或由Host到Device(out事务),或由Device到Host(in事务)。传输总是由Host发起(轮询传输)。回此每条USB总线只能有一个Host。每个包的传输都有一个状态阶段同(同步传输除外),数据接收者可以在其中返回ACK(应答接收),NAK(重试),STALL(错误条件)或什么也没有(混乱数据阶段,设备不可用或已经断开)。

 

      • 主机控制器Driver的工作是什么?

   让主机控制器工作起来,发挥它的潜力。 让控制器发数据、收数据 。主机控制器主要包含以下几步:

    1) 按照主机控制器的要求组织结构体  

       2) 将结构体在合适的时间、放在合适的地方 

       3)  trigger 

       4)  等待完成信号

       主机控制器Driver开发过程就是上面这几步。

2. 关键数据结构

     关键数据结构关系如下图所示:

 

 3. 系统架构 

     EHCI负责处理高速设备,OHCI负责处理全速/低速设备。上面这张图描述了USB控制器在route USB设备时的操作。
     一个port 多个主人,OHCI的角色是companion,伴侣。地位低点。EHCI处理不了再给它处理。 

 

       关于端口逻辑这块需要特别注意,Driver设计者要注意:当前端口正在属于谁。当端口被OHCI所拥有时,你插入个高速设备怎么办?没办法!在没有插入设备时,就不应该让OHCI拥有这个端口。只有EHCI控制器才能识别出设备是全速、高速还是低速。

4. usb_submit_urb

 usb_submit_urb处理流程如下图所示:

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Enhanced Host Controller Interface Specification for Universal Serial Bus<br><br>1. INTRODUCTION...............................................................................................1 <br>1.1 EHCI Product Compliance.................................................................................................................2 <br>1.2 Architectural Overview.......................................................................................................................2 <br>1.2.1 Interface Architecture....................................................................................................................4 <br>1.2.2 EHCI Schedule Data Structures.....................................................................................................5 <br>1.2.3 Root Hub Emulation......................................................................................................................5 <br>2. REGISTER INTERFACE ..................................................................................7 <br>2.1 PCI Configuration Registers (USB)...................................................................................................8 <br>2.1.1 PWRMGT ? PCI Power Management Interface..........................................................................8 <br>2.1.2 CLASSC ? CLASS CODE REGISTER......................................................................................9 <br>2.1.3 USBBASE ? Register Space Base Address Register..................................................................9 <br>2.1.4 SBRN ? Serial Bus Release Number Register.............................................................................9 <br>2.1.5 Frame Length Adjustment Register (FLADJ)..............................................................................10 <br>2.1.6 Port Wake Capability Register (PORTWAKECAP)...................................................................11 <br>2.1.7 USBLEGSUP ? USB Legacy Support Extended Capability.....................................................11 <br>2.1.8 USBLEGCTLSTS ? USB Legacy Support Control/Status........................................................12 <br>2.2 Host Controller Capability Registers...............................................................................................13 <br>2.2.1 CAPLENGTH ? Capability Registers Length...........................................................................13 <br>2.2.2 HCIVERSION ? Host Controller Interface Version Number....................................................14 <br>2.2.3 HCSPARAMS ? Structural Parameters.....................................................................................14 <br>2.2.4 HCCPARAMS ? Capability Parameters....................................................................................15 <br>2.2.5 HCSP-PORTROUTE ? Companion Port Route Description.....................................................16 <br>2.3 Host Controller Operational Registers............................................................................................17 <br>2.3.1 USBCMD ? USB Command Register.......................................................................................18 <br>2.3.2 USBSTS ? USB Status Register................................................................................................21 <br>2.3.3 USBINTR ? USB Interrupt Enable Register..............................................................................22 <br>2.3.4 FRINDEX ? Frame Index Register............................................................................................23 <br>2.3.5 CTRLDSSEGMENT ? Control Data Structure Segment Register............................................24 <br>2.3.6 PERIODICLISTBASE ? Periodic Frame List Base Address Register......................................24 <br>2.3.7 ASYNCLISTADDR ? Current Asynchronous List Address Register.......................................25 <br>2.3.8 CONFIGFLAG ? Configure Flag Register................................................................................25 <br>2.3.9 PORTSC ? Port Status and Control Register.............................................................................26 <br>3. DATA STRUCTURES.....................................................................................31 <br>3.1 Periodic Frame List...........................................................................................................................31 <br>3.2 Asynchronous List Queue Head Pointer..........................................................................................32 <br>3.3 Isochronous (High-Speed) Transfer Descriptor (iTD)....................................................................33 <br>USB 2.0 i <br><br>EHCI Revision 1.0 3/12/2002 <br>3.3.1 Next Link Pointer.........................................................................................................................33 <br>3.3.2 iTD Transaction Status and Control List......................................................................................34 <br>3.3.3 iTD Buffer Page Pointer List (Plus).............................................................................................35 <br>3.4 Split Transaction Isochronous Transfer Descriptor (siTD)...........................................................36 <br>3.4.1 Next Link Pointer.........................................................................................................................37 <br>3.4.2 siTD Endpoint Capabilities/Characteristics.................................................................................37 <br>3.4.3 siTD Transfer State......................................................................................................................38 <br>3.4.4 siTD Buffer Pointer List (plus)....................................................................................................39 <br>3.4.5 siTD Back Link Pointer...............................................................................................................40 <br>3.5 Queue Element Transfer Descriptor (qTD).....................................................................................40 <br>3.5.1 Next qTD Pointer.........................................................................................................................41 <br>3.5.2 Alternate Next qTD Pointer.........................................................................................................41 <br>3.5.3 qTD Token...................................................................................................................................42 <br>3.5.4 qTD Buffer Page Pointer List......................................................................................................45 <br>3.6 Queue Head........................................................................................................................................46 <br>3.6.1 Queue Head Horizontal Link Pointer...........................................................................................46 <br>3.6.2 Endpoint Capabilities/Characteristics..........................................................................................47 <br>3.6.3 Transfer Overlay..........................................................................................................................49 <br>3.7 Periodic Frame Span Traversal Node (FSTN)................................................................................51 <br>3.7.1 FSTN Normal Path Pointer..........................................................................................................51 <br>3.7.2 FSTN Back Path Link Pointer......................................................................................................52 <br>4. OPERATIONAL MODEL................................................................................53 <br>4.1 Host Controller Initialization............................................................................................................53 <br>4.2 Port Routing and Control..................................................................................................................54 <br>4.2.1 Port Routing Control via EHCI Configured (CF) Bit..................................................................55 <br>4.2.2 Port Routing Control via PortOwner and Disconnect Event.......................................................56 <br>4.2.3 Example Port Routing State Machine..........................................................................................57 <br>4.2.4 Port Power....................................................................................................................................57 <br>4.2.5 Port Reporting Over-Current........................................................................................................58 <br>4.3 Suspend/Resume................................................................................................................................59 <br>4.3.1 Port Suspend/Resume..................................................................................................................59 <br>4.4 Schedule Traversal Rules..................................................................................................................61 <br>4.4.1 Example - Preserving Micro-Frame Integrity..............................................................................62 <br>4.5 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries..................................................64 <br>4.6 Periodic Schedule...............................................................................................................................66 <br>4.7 Managing Isochronous Transfers Using iTDs.................................................................................67 <br>4.7.1 Host Controller Operational Model for iTDs...............................................................................67 <br>4.7.2 Software Operational Model for iTDs.........................................................................................69 <br>4.8 Asynchronous Schedule.....................................................................................................................71 <br>4.8.1 Adding Queue Heads to Asynchronous Schedule........................................................................71 <br>4.8.2 Removing Queue Heads from Asynchronous Schedule..............................................................72 <br>4.8.3 Empty Asynchronous Schedule Detection...................................................................................74 <br>ii USB 2.0 <br><br>EHCI Revision 1.0 3/12/2002 <br>4.8.4 Restarting Asynchronous Schedule Before EOF.........................................................................74 <br>4.8.5 Asynchronous Schedule Traversal : Start Event..........................................................................76 <br>4.8.6 Reclamation Status Bit (USBSTS Register)................................................................................77 <br>4.9 Operational Model for Nak Counter................................................................................................77 <br>4.9.1 Nak Count Reload Control...........................................................................................................78 <br>4.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads....................................................79 <br>4.10.1 Fetch Queue Head........................................................................................................................80 <br>4.10.2 Advance Queue............................................................................................................................81 <br>4.10.3 Execute Transaction.....................................................................................................................81 <br>4.10.4 Write Back qTD...........................................................................................................................86 <br>4.10.5 Follow Queue Head Horizontal Pointer.......................................................................................86 <br>4.10.6 Buffer Pointer List Use for Data Streaming with qTDs...............................................................86 <br>4.10.7 Adding Interrupt Queue Heads to the Periodic Schedule.............................................................88 <br>4.10.8 Managing Transfer Complete Interrupts from Queue Heads.......................................................88 <br>4.11 Ping Control.......................................................................................................................................88 <br>4.12 Split Transactions..............................................................................................................................89 <br>4.12.1 Split Transactions for Asynchronous Transfers...........................................................................90 <br>4.12.2 Split Transaction Interrupt...........................................................................................................92 <br>4.12.3 Split Transaction Isochronous....................................................................................................103 <br>4.13 Host Controller Pause......................................................................................................................114 <br>4.14 Port Test Modes...............................................................................................................................114 <br>4.15 Interrupts..........................................................................................................................................115 <br>4.15.1 Transfer/Transaction Based Interrupts.......................................................................................115 <br>4.15.2 Host Controller Event Interrupts................................................................................................117 <br>5. EHCI EXTENDED CAPABILITIES...............................................................121 <br>5.1 EHCI Extended Capability: Pre-OS to OS Handoff Synchronization........................................121 <br>APPENDIX A. EHCI PCI POWER MANAGEMENT INTERFACE......................125 <br>A.1 PCI Power Management Register Interface..................................................................................125 <br>A.1.1 Power State Transitions.............................................................................................................126 <br>A.1.2 Power State Definitions.............................................................................................................126 <br>A.1.3 PCI PME# Signal.......................................................................................................................127 <br>APPENDIX B. EHCI 64-BIT DATA STRUCTURES............................................129 <br>APPENDIX C. DEBUG PORT.............................................................................133 <br>C.1 Locating the Debug Port..................................................................................................................133 <br>C.2 Using the Debug Port Fields............................................................................................................134 <br>C.3 USB2 Debug Port Register Interface..............................................................................................134 <br>USB 2.0 iii <br><br>EHCI Revision 1.0 3/12/2002 <br>C.3.1 Debug Port Control Register......................................................................................................135 <br>C.3.2 USB PIDs Register.....................................................................................................................137 <br>C.3.3 Data Buffer.................................................................................................................................137 <br>C.3.4 Device Address Register............................................................................................................138 <br>C.4 Operational Model...........................................................................................................................138 <br>C.4.1 OUT/SETUP Transactions.........................................................................................................139 <br>C.4.2 IN transactions...........................................................................................................................139 <br>C.4.3 Debug Software Startup.............................................................................................................139 <br>C.4.4 Finding the Debug Peripheral....................................................................................................140 <br>APPENDIX D. HIGH BANDWIDTH ISOCHRONOUS RULES............................141 <br> <br>

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