四组6比特的并行数据转换成串行数据

今天随手写了一个四组6比特的并行数据转换成串行数据的模块，这里贴出来跟大家分享一下

环境：ISE10.1   synplicity 9.6.2综合  modelsim6.5仿真

程序如下：

module parallel(clk,rst,r1,r2,r3,r4,dout,flag1,flag2,flag3,flag4);//6位并串转换程序

input clk,rst;

input[5:0]r1,r2,r3,r4;//6bit input signal

output dout,flag1,flag2,flag3,flag4;

reg dout,flag1,flag2,flag3,flag4;

reg[1:0]counter_4;

reg[2:0]couner_6bit;

always @ (posedge clk or negedge rst )begin//have a problem

  if(!rst)

    begin

        counter_4<=2'b00;

                     couner_6bit<=3'b00;

                         flag1<=0; 标志四组数据转行的情况，用于检测转行的正确性

                              flag2<=0;

                              flag3<=0;

                              flag4<=0;

                    end

   else

         begin

         case(counter_4)

           2'b00:

           begin

       dout<=r1[couner_6bit];

                                     flag1<=1;

                                     flag2<=0;

                                     flag3<=0;

                                     flag4<=0;

                             if(couner_6bit==3'b101)begin

                               counter_4=counter_4+1;

                                     couner_6bit<=3'b00;

                               end

                            else couner_6bit=couner_6bit+1;

                   end

          2'b01:

          begin

       dout<=r2[couner_6bit];

                                     flag1<=0;

                                     flag2<=1;

                                     flag3<=0;

                                     flag4<=0;

                             if(couner_6bit==3'b101)begin

                               counter_4=counter_4+1;

                                     couner_6bit<=3'b00;

                            end

                            else couner_6bit=couner_6bit+1;

           end

          2'b10:

          begin

       dout<=r3[couner_6bit];

                                     flag1<=0;

                                     flag2<=0;

                                     flag3<=1;

                                     flag4<=0;

                            if(couner_6bit==3'b101)begin

                               counter_4=counter_4+1;

                                     couner_6bit<=3'b00;

                            end

                            else couner_6bit=couner_6bit+1;

           end

          2'b11:

          begin

       dout<=r4[couner_6bit];

                                     flag1<=0;

                                     flag2<=0;

                                     flag3<=0;

                                     flag4<=1;

                             if(couner_6bit==3'b101)begin

                               counter_4=counter_4+1;

                                     couner_6bit<=3'b00;

                            end

                            else couner_6bit=couner_6bit+1;

           end

         default:

         begin                 

                     counter_4<=2'b00;

                     couner_6bit<=3'b00;

                                     flag1<=0;

                                     flag2<=0;

                                     flag3<=0;

                                     flag4<=0;

   end

 endcase

   end

         end

endmodule

测试文件：

         initial begin

                   // Initialize Inputs

                   clk = 0;

                   rst = 0;

                   r1 = 0;

                   r2 = 0;

                   r3 = 0;

                   r4 = 0;

                   #10;

                   rst=1;      

                   #20;

                   r1=6'b100000;

                   r2=6'b000011;

                   r3=6'b011100;

                   r4=6'b011110;

         end

         always #5 clk=~clk;

endmodule

仿真结果：数据从右到左读出

 

修改程序：红色表示修改处

 

module parallel(clk,rst,r1,r2,r3,r4,dout,flag1,flag2,flag3,flag4);//6位并串转换程序

input clk,rst;

input[5:0]r1,r2,r3,r4;//6bit input signal

output dout,flag1,flag2,flag3,flag4;

reg dout,flag1,flag2,flag3,flag4;

reg[1:0]counter_4;

reg[2:0]couner_6bit=3'b101;

always @ (posedge clk or negedge rst )begin//have a problem

  if(!rst)

    begin

        counter_4<=2'b00;

                     couner_6bit<=3'b101;

                         flag1<=0;

                                     flag2<=0;

                                     flag3<=0;

                                     flag4<=0;

                    end

   else

         begin

         case(counter_4)

           2'b00:

           begin

       dout<=r1[couner_6bit];

                                     flag1<=1;

                                     flag2<=0;

                                     flag3<=0;

                                     flag4<=0;

                             if(couner_6bit==3'b000)begin

                               counter_4=counter_4+1;

                                     couner_6bit<=3'b101;

                               end

                            else couner_6bit=couner_6bit-1;

                   end

          2'b01:

          begin

       dout<=r2[couner_6bit];

                                     flag1<=0;

                                     flag2<=1;

                                     flag3<=0;

                                     flag4<=0;

                             if(couner_6bit==3'b000)begin

                               counter_4=counter_4+1;

                                     couner_6bit<=3'b101;

                               end

                            else couner_6bit=couner_6bit-1;

           end

          2'b10:

          begin

       dout<=r3[couner_6bit];

                                     flag1<=0;

                                     flag2<=0;

                                     flag3<=1;

                                     flag4<=0;

                            if(couner_6bit==3'b000)begin

                               counter_4=counter_4+1;

                                     couner_6bit<=3'b101;

                               end

                            else couner_6bit=couner_6bit-1;

           end

          2'b11:

          begin

       dout<=r4[couner_6bit];

                                     flag1<=0;

                                     flag2<=0;

                                     flag3<=0;

                                     flag4<=1;

                             if(couner_6bit==3'b000)begin

                               counter_4=counter_4+1;

                                     couner_6bit<=3'b101;

                               end

                            else couner_6bit=couner_6bit-1;

           end

         default:

         begin                

                     counter_4<=2'b00;

                     couner_6bit<=3'b101;

                                     flag1<=0;

                                     flag2<=0;

                                     flag3<=0;

                                     flag4<=0;

   end

 endcase

   end

         end

endmodule

 

则结果从左到右输出