VHDL 整数转化为向量 integer to std_logic_vector
首先包含std_logic_arith
然后:(举例分析)
signal
input_1 :
integer
;
signal
output_1 :
std_logic_vector
(3
downto
0);
output_1 <= conv_std_logic_vector(input_1, output_1'length);
首先包含std_logic_arith
然后:(举例分析)
signal
input_1 :
integer
;
signal
output_1 :
std_logic_vector
(3
downto
0);
output_1 <= conv_std_logic_vector(input_1, output_1'length);