练习六 函数

源代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    16:17:53 07/26/2019 
// Design Name: 
// Module Name:    tryfunct_test 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module tryfunct_test(
							clk,
							n,
							result,
							reset
    );
	output [31:0]result;
	input [3:0]n;
	input reset,clk;
	reg[31:0]result;
	
	always @(posedge clk)	//clk的上升沿触发同步运算
		begin
			if(!reset)
				result <= 0;
			else
				begin
					result <= n *factorial(n)/((n*2)+1);
				end	//verilog 在整数除法运算结果中不考虑余数
		end
	
	function [31:0]factorial;	//函数定义，返回的是一个32位的数
		input [3:0]operand;		//输入只有一个4位的操作数
		reg [3:0]index;			//函数内部计数用中间变量
		begin
			factorial = operand ?1:0;//先定义操作数为零时函数的输出为零，不为零时为1
			for(index = 2;index <= operand;index = index+1)
			factorial = index * factorial;//表示阶乘的算数迭代运算
		end
	endfunction

endmodule

测试代码

`timescale 1ns / 100ps
`define clk_cycle 50

// Company: 
// Engineer:
//
// Create Date:   16:50:48 07/26/2019
// Design Name:   tryfunct_test
// Module Name:   D:/FPGA/project/tryfunct_test/testbench/vtf_tryfunct_test.v
// Project Name:  tryfunct_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: tryfunct_test
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module vtf_tryfunct_test;

	// Inputs
	reg clk;
	reg [3:0] n,i;
	reg reset;

	// Outputs
	wire [31:0] result;

	// Instantiate the Unit Under Test (UUT)
	tryfunct_test uut (
		.clk(clk), 
		.n(n), 
		.result(result), 
		.reset(reset)
	);

	always #`clk_cycle clk = ~clk;
	
	initial begin
		// Initialize Inputs
		clk = 0;
		n = 0;
		reset = 1;
		#100	reset = 0;
		#100	reset = 1;
		for(i = 0;i<=15;i=i+1)
			begin
				#200	n = i;
			end
		#100	$stop;
		

		
	end
      
endmodule

仿真波形