TI AM65x/DRA80xM Ethernet

1 Cortex-A53
CGT: The PRU Code Generation Tool
CPTS: Common Platform Time Sync
PRU_ICSSGn: Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit, where n = 0 to 2.
PRU_ICSSG2 includes 2 ethernet controllers, and each controller can use SerDes or RGMII.
PRU is a software EMAC, which uses ARM Cortex-A53 UDMA implements DMA channel.

2 Cortex-R5F
CPSW: Common Platform Ethernet Switch
lwIP stack

In switch mode, the CPSW (TI Common Platform Ethernet Switch) acts like a true Ethernet switch. Any port traffic can be routed to any port based on VLAN, port or address rules.
The host port has some special rules so that it can act as an endpoint or a bridge extender depending on target use case.

Each CPTS EST 22-bit fetch command consists of a 14-bit fetch count (14 MSB’s) and an 8-bit priority fetch allow (8 LSB’s) that will be applied for the fetch count time in wireside clocks. Capture frame using wireshark at the PC to see how EST work. The frames will be on the wire only at scheduled time and a periodic burst of frames will be seen every 500 milli seconds.