除法器勘误

1、c时序逻辑 除法器勘误
原文链接：https://blog.csdn.net/aaaaaaaa585/article/details/118300782

module Divider_0#(
	 parameter	DIVISOR_WIDTH		= 32,
	 parameter	DIVIDEND_WIDTH		= 32
)(
	input									clk_i,
	input									rst_i,
	//------------------------------------------------//
	input			[DIVISOR_WIDTH-1:0]		divisor_i,
	input			[DIVIDEND_WIDTH-1:0]	dividend_i,
	input									cal_en_i,
	//------------------------------------------------//
	output	reg		[DIVISOR_WIDTH-1:0]		quotient_o,	
	output	reg		[DIVIDEND_WIDTH-1:0]	remainders_o,
	output	reg								cal_valid_o
);

(* keep = "TRUE" *) reg	[DIVISOR_WIDTH+DIVIDEND_WIDTH:0]		tempa	[DIVISOR_WIDTH : 0];
(* keep = "TRUE" *) reg	[DIVISOR_WIDTH+DIVIDEND_WIDTH-1:0]		tempb	[DIVISOR_WIDTH : 0];
(* keep = "TRUE" *) reg	[DIVISOR_WIDTH:0]		cal_valid_dly;
//integer	i;
genvar i;
generate

always @(posedge clk_i)begin 
	if(rst_i == 1'b1)begin
		tempa[0] <= 'd0; 
		tempb[0] <= 'd0;
	end
	else if(cal_en_i == 1'b1)begin
		tempa[0] <= {{DIVIDEND_WIDTH{1'b0}},divisor_i,1'b0};
		tempb[0] <= {dividend_i,{DIVISOR_WIDTH{1'b0}}}; 
	end
	else begin
		tempa[0] <= tempa[0];
		tempb[0] <= tempb[0];
	end 
end

reg	[DIVISOR_WIDTH:0] dbg;

for(i = 0;i < DIVISOR_WIDTH;i = i + 1)begin
	always @(posedge clk_i)begin 
		if(tempa[i][DIVISOR_WIDTH + DIVIDEND_WIDTH : DIVISOR_WIDTH ] >= tempb[i][DIVISOR_WIDTH +: DIVIDEND_WIDTH])begin
			tempa[i+1] <= ((tempa[i] - tempb[i] )<<1) + 1'b1;
			tempb[i+1] <= tempb[i];
			dbg[i+1] <= 1'b1;
		end
		else begin
			tempa[i+1] <= tempa[i]<<1;
			tempb[i+1] <= tempb[i];
			dbg[i+1] <= 1'b0;
		end
	end
end

always @(posedge clk_i)begin 
	quotient_o	<= tempa[DIVISOR_WIDTH][0 +: DIVISOR_WIDTH];
	remainders_o	<= tempa[DIVISOR_WIDTH][DIVISOR_WIDTH+1 +: DIVIDEND_WIDTH];
end

always @(posedge clk_i)begin 
	cal_valid_dly <= {cal_valid_dly[0 +: DIVISOR_WIDTH],cal_en_i};
	cal_valid_o <= cal_valid_dly[DIVISOR_WIDTH];
end	

endgenerate

endmodule