Verilog LED

module LED
(
 input clk,//50M
 input rst_n, 
 output led
);
reg [22:0] cnt; 

parameter LED_CNT = 49_999_999;
always@(posedge clk or negedge rst_n)
begin
 if(!rst_n)
  cnt <= 23'd0;
 else if(cnt < LED_CNT)
  cnt <= cnt + 1'b1;
 else
  cnt <= 23'd0;
end
assign led = (cnt == 23'd49_99999)   1'b1 : 1'b0;
endmodule