Verilog语言led灯的简单历程

//
//1.点亮一颗灯
/light one/
//module liushuideng(
//input clk,
//input rst,
//output led
//    );
//reg led;

//always @(posedge clk or negedge rst)
//if(!rst) led <= 1'b1;
//else led <= 1'b0;

//endmodule

//2.点亮八颗灯/
//module liushuideng(
//input clk,
//input rst,
//output reg[7:0] led
//);

//always@(posedge clk or negedge rst)
//if(!rst) led <= 8'b1111_1111;
//else led <= 8'b0000_0000;

//endmodule 

//3.延迟点亮八颗灯//
//module liushuideng(
//input clk,
//input rst,
//output reg[7:0] led
//);

//reg[27:0] cnt; 

//always@(posedge clk or negedge rst)
//if(!rst) cnt <= 28'd0;
//else cnt <= cnt+1'b1;

//always@(posedge clk or negedge rst)
//if(!rst) led <= 8'b1111_1111;
//else if(cnt == 28'hfffffff) 
//led <= 8'b0000_0000;

//endmodule

//4.八个灯闪闪
//module liushuideng(
//input clk,
//input rst,
//output reg[7:0] led
//);
//reg[27:0] cnt;

//always@(posedge clk or negedge rst)
//if(!rst) cnt <= 28'd0;
//else if(cnt == 28'hfffffff) cnt <= 28'd0;
//else cnt <= cnt +1'b1;

//always@(posedge clk or negedge rst)
//if(!rst) led <= 8'b1111_1111;
//else if(cnt == 28'hffffffe) 
//led <= ~led;

//endmodule

//5.循环点亮led灯
//module liushuideng(
//input clk,
//input rst,
//output reg[7:0] led
//);

//reg [27:0] cnt;

//always@(posedge clk or negedge rst)
//if(!rst) cnt <= 28'd0;
//else if(cnt == 28'hfffffff) cnt <= 28'd0;
//else cnt <= cnt+1'b1;

//always@(posedge clk or negedge rst)
//if(!rst) led <= 8'b1111_1110;
//else if(cnt == 28'hffffff) led <={led[6:0],led[7]};

//endmodule 

这些都是很简单的例子，只是想说，一点一点慢慢来，从点亮一颗到8颗，再到延迟亮，循环亮，由易到难实现，从中一点一点进步